Dual-PLL Frequency Synthesizer for Jitter-Tolerant Wireless Clocks
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Solution Overview
Problem
Wireless communication systems face excessive clock jitter due to long optical links and clock recovery algorithms, degrading the quality of received and transmitted signals.
Innovation Solution
A frequency synthesizer with first and second phase-locked loops, including a digital phase/frequency detector, digitally-controlled oscillator, and voltage-controlled oscillator, which generates high frequency resolution, reduces spurious signals, and low phase noise, even with significant phase jitter in the network clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the optical link length is increased to reduce RF losses, then the base station structure becomes more flexible, but clock jitter increases significantly
Solution Approach 1:
The patent divides the single PLL into two separate PLLs: a first PLL for generating a reference signal from the network clock, and a second PLL for generating the output signal. This segmentation allows the first PLL to filter out jitter from the network clock while the second PLL generates the final signal, thus resolving the contradiction between structural flexibility and clock jitter.
Solution Approach 2:
The first PLL acts as an intermediary between the network clock and the second PLL. It processes the network clock signal to generate a clean reference signal with reduced jitter, which then feeds into the second PLL. This intermediary structure enables the system to maintain flexibility while eliminating the harmful jitter effect.
2Device complexity
If conventional single PLL synthesizers are used, then the device complexity is low, but phase noise and spurious signals are excessive
Solution Approach 1:
The patent segments the frequency synthesis function into two independent PLLs: the first PLL generates a reference signal with filtered phase noise, and the second PLL generates the final output signal. This segmentation reduces spurious signals and phase noise in the output while maintaining reasonable device complexity through modular design.
Solution Approach 2:
Both PLLs employ feedback mechanisms where the output of each PLL is fed back to its phase detector, creating closed-loop control that suppresses phase noise and spurious signals. The dual-PLL structure with feedback provides better noise performance than a single PLL while keeping the overall system complexity manageable.
3Reliability
If the loop bandwidth is narrowed to reduce jitter, then clock jitter is reduced, but the response speed and adaptability decrease
Solution Approach 1:
The patent segments the filtering function from the frequency generation function by using two separate PLLs. The first PLL can use a narrow loop bandwidth to effectively filter jitter from the network clock, while the second PLL can use a broader loop bandwidth to maintain fast response speed. This segmentation resolves the contradiction between jitter reduction and response speed.
Solution Approach 2:
The patent adds a temporal dimension to the solution by processing signals in two sequential stages through two PLLs. The first PLL operates with narrow bandwidth for jitter filtering over time, while the second PLL operates with broader bandwidth for fast frequency switching. This dimensional approach allows both jitter reduction and fast response to be achieved simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The synthesizer effectively reduces phase noise and spurious signals, improving signal quality by decoupling phase jitter from the output signal and allowing broader loop bandwidths, thus enhancing the performance of wireless communication systems.
Implementation Method 1
The synthesizer includes first and second phase-locked loops
Implementation Method 2
a digital phase/frequency detector
Implementation Method 3
digitally-controlled oscillator
Implementation Method 4
voltage-controlled oscillator
Data Source
AI summary
Synthesizers are configured with first and second phase-locked loops (PLL's). The first PLL is arranged to include a digitally-controlled oscillator (DCO) and to respond to an input signal to provide a reference signal with a plurality of selectable reference frequencies. The second PLL is arranged to include a voltage-controlled oscillator (VCO) to thereby provide output signals in response to the reference signal. This synthesizer structure is particularly effective when responding to a noisy input signal as may be the case, for example, in wireless communication systems that provide a network clock to transceivers through lengthy optical links.