Dual Power Management Circuit Design for Low Power State
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Solution Overview
Problem
Existing power management integrated circuits (PMICs) face challenges in efficiently reducing power consumption during low power states without completely shutting down functions, which can lead to reduced performance and operational quality.
Innovation Solution
The implementation of dual circuit designs within PMICs, where one set of circuits is optimized for normal operations and another for low power modes, allowing for reduced power consumption while maintaining essential functionalities such as voltage monitoring, current monitoring, and temperature sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If functions are completely shut down during low power states, then power consumption is reduced, but performance and operational quality deteriorate
Solution Approach 1:
The patent segments the power management circuit into multiple independent circuit sets, each optimized for different power states. This allows selective activation of circuit subsets based on power state requirements, enabling the system to maintain essential functions during low power states while reducing overall power consumption. The segmentation principle resolves the contradiction by allowing partial operation rather than complete shutdown or full operation.
Solution Approach 2:
The patent implements dynamic circuit configuration where the active circuit set changes based on the power state. During low power states, a subset of circuits is activated while others remain inactive, and this configuration dynamically adjusts when transitioning between power states. This dynamic approach enables the system to optimize power consumption while maintaining necessary operational quality by activating only the minimum required circuits.
2Device complexity
If a single circuit design is used for both normal and low power modes, then device complexity is reduced, but power consumption cannot be optimized
Solution Approach 1:
The patent creates a universal power management circuit architecture that can operate in multiple power states by activating different subsets of circuits. The same physical circuit infrastructure serves both normal and low power modes, with the distinction being which specific circuits are active. This multi-functionality approach allows the system to optimize power consumption without requiring entirely separate circuit designs for each mode.
Solution Approach 2:
The patent applies local quality optimization by having different circuits within the same power management system optimized for different operating conditions. Each circuit subset is designed with specific characteristics suited for its intended power state, while the overall system maintains a unified architecture. This allows power consumption optimization at the local circuit level without increasing overall device complexity.
3Reliability
If all circuits remain active during low power states, then operational quality is maintained, but power consumption targets are not met
Solution Approach 1:
The patent extracts and isolates the essential functions that must remain active during low power states from the complete circuit set. By identifying and separating the minimum required circuits for maintaining operational quality, the system can deactivate all non-essential circuits during low power states. This extraction approach ensures power consumption targets are met while preserving necessary operational quality.
Solution Approach 2:
The patent implements partial action by activating only the necessary subset of circuits during low power states rather than all circuits. This partial operation allows the system to meet stringent power consumption targets while maintaining sufficient operational quality for critical functions. The approach accepts reduced performance in non-critical areas to achieve overall power optimization.
Data Source
AI summary
A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.