Dual Pointer Shared Memory Ring for Multi-Process Data Communication
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Solution Overview
Problem
Existing methods for communication between a host device and an external peripheral device are inefficient when multiple processes are involved, leading to resource wastage and increased latency due to the need for multiple interface memory rings or additional data copying.
Innovation Solution
A method where a processor device uses a shared memory region for data communication, with multiple processes accessing it through separate pointers, and indicating the lower pointer to the peripheral device upon completion or increment, allowing simultaneous processing and efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple interface memory rings are configured for each process, then data communication to multiple processes is enabled, but resource utilization becomes inefficient
Solution Approach 1:
The patent merges multiple interface memory rings into a single shared memory ring that serves multiple processes. Instead of allocating separate memory rings for each process, the system uses one common memory ring with a shared buffer, reducing the total memory resources required while maintaining the ability to communicate data to multiple processes simultaneously.
Solution Approach 2:
The shared memory ring is designed to be universal, serving multiple processes through a common interface. The memory ring can be accessed by different processes using their respective process identifiers, allowing a single memory structure to perform the function of multiple dedicated memory rings would otherwise be needed.
2Device complexity
If one interface memory ring is used with master process copying data, then resource utilization improves, but additional latency is introduced for the slave process
Solution Approach 1:
The peripheral device performs preliminary action by directly writing data into the shared memory ring for both processes simultaneously, rather than requiring the master process to copy data after the slave process has indicated its readiness. This eliminates the sequential copying step and reduces latency for the slave process while maintaining efficient resource utilization.
Solution Approach 2:
The shared memory ring acts as an intermediary that directly receives data from the peripheral device and makes it available to multiple processes without requiring intermediate copying operations. The memory ring serves as a common intermediary buffer that eliminates the need for master-process-mediated data copying, thereby reducing latency.
3Productivity
If the peripheral device writes data directly into shared memory, then communication efficiency improves, but data management complexity increases
Solution Approach 1:
The system implements feedback mechanisms where processes indicate their processing status and pointer positions back to the peripheral device. This feedback allows the peripheral device to manage data writing efficiently by knowing which processes have processed which data entries, enabling direct writes to the shared memory without causing data overwrites or losses, thus maintaining high communication efficiency while managing complexity through coordinated feedback loops.
Data Source
AI summary
A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory region. Based on a first pointer to the shared memory region, a first process executed by the processor device processes a first group of the data entries. Based on a second pointer to the shared memory region, a second process executed by the processor device processes a second group of the data entries. The second process indicates the second pointer to the first process. The first process indicates a lower one of the first pointer and the second pointer to the peripheral device.