Dual Poly Pitch IC Structure for 10nm Node Fabrication
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Solution Overview
Problem
The scaling of features in integrated circuits to the 10 nanometer node and beyond is hindered by variability in conventional fabrication processes, limiting the ability to further miniaturize and increase device density.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor fabrication, combined with the use of dual poly pitches and advanced doping techniques, to enhance line density and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node and below
Solution Approach 1:
The fabrication process is divided into multiple sequential stages including pitch doubling, pitch quartering, and merged fin pitch quartering. Each stage breaks down the complex task of creating sub-10nm features into manageable steps with intermediate structures, allowing precise control at each phase rather than attempting single-step patterning
Solution Approach 2:
Mandrel structures and spacer layers are formed in advance before the final pattern transfer. The pitch doubling and quartering processes use preliminary mandrel formation followed by spacer deposition and mandrel removal, preparing the structure step-by-step to achieve the required precision before final transistor fabrication
2Quantity of substance
If feature size is reduced to increase device density, then quantity of devices increases, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
Spacer structures serve as intermediary elements between the lithographically defined mandrels and the final transistor gates. The spacers provide a controlled intermediate dimension that is determined by conformal deposition thickness rather than direct lithography, achieving precision at the spacer width that translates to controlled final feature dimensions
Solution Approach 2:
The process transforms the critical dimension control from being lithography-limited to deposition-limited by using conformal spacer formation. By controlling the spacer layer thickness through atomic layer deposition or chemical vapor deposition parameters, the final feature pitch is precisely controlled independent of lithographic resolution limits
3Manufacturing precision
If pitch quartering and merged fin pitch quartering are implemented, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Multiple pitch quartering operations are merged into a single integrated process flow. The merged fin pitch quartering combines the formation of different fin pitch regions in one sequence, where spacers are formed and selectively removed to create both tight and wide pitch areas without requiring separate patterning cycles for each region
4Quantity of substance
If tighter pitch and spacing are achieved in semiconductor fins, then device density increases, but ease of manufacture decreases
Solution Approach 1:
The spacer structures self-align to the mandrel features through conformal deposition, automatically establishing the correct pitch relationships without requiring additional alignment steps. The process uses self-aligned spacer formation where the spacer width is determined by deposition thickness and anisotropic etching, eliminating the need for separate alignment and focusing operations
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of logic gate structures having a first pitch between adjacent ones of the first plurality of logic gate structures. The integrated circuit structure also includes a second plurality of logic gate structures having a second pitch between adjacent ones of the second plurality of logic gate structures. The second pitch is greater than the first pitch.