Dual Polycide Gate CMOS Device Preventing Dopant Inter-Diffusion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In CMOS devices, dopant inter-diffusion between NMOS and PMOS gates in the peripheral circuit region leads to gate depletion effects, degrading electrical characteristics and potentially causing transistor malfunction due to increased integration density.
Innovation Solution
The CMOS device features dual polycide gates with n+ and p+ polycide gates formed in separated regions, using a stack layer including a gate insulation layer, a silicon layer with implanted impurities, and a metal silicide layer, with bit-lines forming a bridge structure to prevent dopant inter-diffusion, specifically using tungsten silicide and selective ion-implantation of Phosphorus or Arsenic for n-type and Boron or Boron difluoride for p-type impurities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual polycide gates are formed in adjacent regions to achieve low resistance in highly integrated devices, then electrical conductivity is improved, but dopant inter-diffusion occurs between gates causing gate depletion effects
Solution Approach 1:
An undoped polysilicon layer is introduced as an intermediary barrier between the n+ and p+ doped polysilicon layers. This intermediate layer prevents direct contact between oppositely doped regions, blocking dopant inter-diffusion while maintaining the low-resistance polycide gate structure. The undoped polysilicon acts as a diffusion barrier that preserves gate characteristics without compromising electrical conductivity.
Solution Approach 2:
The gate structure is segmented into multiple distinct layers: n+ doped polysilicon, undoped polysilicon, p+ doped polysilicon, and metal silicide. This segmentation separates the doped regions that would otherwise be in direct contact, preventing harmful dopant inter-diffusion while maintaining the functional integrity of the dual polycide gate structure for low resistance.
2Productivity
If integration density is increased to improve device functionality, then device capability is improved, but dopant inter-diffusion between adjacent gates increases causing electrical degradation
Solution Approach 1:
The undoped polysilicon layer serves as a mediator that enables high integration density by allowing adjacent n+ and p+ polycide gates to be placed closer together while preventing dopant inter-diffusion. This intermediary structure maintains electrical characteristic stability even as integration density increases, enabling higher device capability without degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents dopant inter-diffusion and gate depletion effects, stabilizing gate characteristics and improving device reliability and yield, enabling the manufacturing of highly integrated devices without significant electrical degradation.
Implementation Method 1
a metal silicide layer 6 and a hard mask layer 7 are sequentially formed on polysilicon layers 5a and 5b
Implementation Method 2
masking process and ion implant process as well-known are performed to form P-well 3a and N-well 3b
Data Source
AI summary
A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes.