Dual-Port SRAM Metal Layer Layout for Low-Resistance Bit-Lines
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Solution Overview
Problem
In deep sub-micron technology, embedded SRAM bit-lines face high resistance issues due to metal pitch limitations, leading to IR drop concerns and reduced cell speed, especially in dual-port SRAMs, which require complex BEOL metal routing for multiple word-lines.
Innovation Solution
A dual-port SRAM structure is designed with bit-lines and word-lines on different metal layers, sharing via connections to simplify circuit design and reduce metal resistance, using a multi-level metal layer arrangement with symmetrical device patterns to optimize routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bit-lines are placed in the lowest level metallization layer (M1) to reduce bit-line capacitance, then capacitance is reduced, but metal pitch is pushed to limitation and resistance increases
Solution Approach 1:
The patent moves bit-lines from the lowest metal layer (M1) to higher metal layers (M2-M6), utilizing the vertical dimension to resolve the conflict between capacitance reduction and resistance control. This dimensional transition allows bit-lines to achieve both low capacitance through proximity to transistors and low resistance through wider metal traces available in upper layers.
2Reliability
If metal width is increased to reduce metal resistance, then resistance is reduced, but routing density is compromised
Solution Approach 1:
The patent distributes bit-lines across multiple metal layers (M2-M6) rather than concentrating them in a single layer. This vertical distribution enables each bit-line to have sufficient width for low resistance while maintaining overall routing density through efficient use of the three-dimensional metal interconnect space.
3Productivity
If dual-port SRAM uses multiple word-lines routing, then parallel operation capability is improved, but BEOL metal routing complexity increases
Solution Approach 1:
The patent implements multiple word-lines (WL-A and WL-B) on different metal layers, enabling parallel read/write operations across dual ports while distributing routing complexity across the vertical dimension. This layered approach allows independent control of multiple word-lines without excessive planar routing complexity.
Data Source
AI summary
A dual-port memory structure includes a plurality of grouped-cells, a first bit-line pair and a second bit-line pair. The grouped-cells are in a word-line routing direction, wherein each grouped-cell comprises a plurality of dual-port memory cells adjacently disposed and is placed in the word-line routing direction. The dual-port memory cells of each grouped-cell share the first bit-line pair and the second bit-line pair, and the first bit-line pair and the second bit-line pair are located on different two of a plurality of level metal layers.