Dual-Port Memory Concurrent Access Control via Dynamic Word Line Pulse Widths
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Solution Overview
Problem
Dual-port memory is vulnerable to intermittent failures due to port-to-port interactions, leading to quality issues and increased defective parts per million (DPPM), making it challenging to test and manufacture effectively.
Innovation Solution
The implementation of a dual-port memory system with a first memory array, address decoders, and control circuits that generate word line signals for concurrent access, along with multiplexer circuits using stacked transistors to manage bit lines and prevent concurrent write operations, ensuring correct read and write operations by adjusting pulse widths and transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port memory allows concurrent access to two ports of memory cells, then access speed and productivity are improved, but reliability deteriorates due to port-to-port interactions causing intermittent failures
Solution Approach 1:
The patent segments the concurrent access control into distinct control signals: a first control signal for the first port and a second control signal for the second port. These control signals independently manage the access operations, allowing the system to maintain high productivity through concurrent access while improving reliability by preventing port-to-port interactions through separate control mechanisms
Solution Approach 2:
The patent introduces control signals as intermediary elements between the access requests and the memory cell operations. The first control signal and second control signal act as mediators that coordinate the concurrent access operations, enabling fast access speeds while preventing harmful interactions between ports through proper timing and control
2Productivity
If the memory system implements concurrent read operations to improve throughput, then productivity increases, but the complexity of controlling and preventing interaction failures increases
Solution Approach 1:
The patent segments the control function by providing separate control signals for each port's access operations. This segmentation allows independent control of each port's read operations, simplifying the overall control logic while enabling concurrent access for high throughput
Solution Approach 2:
The patent implements preliminary action by establishing control signals before the actual memory access operations occur. The first control signal and second control signal are generated in advance to coordinate the concurrent read operations, preventing interactions before they can cause failures
3Reliability
If word line pulse widths are extended to ensure complete read operations during concurrent access, then reliability improves, but the time for subsequent operations increases
Solution Approach 1:
The patent applies dynamics by making the word line pulse widths adjustable rather than fixed. The pulse widths can be dynamically optimized based on the specific access patterns and concurrent operation requirements, ensuring reliable reads when needed while minimizing overall operation time
Solution Approach 2:
The patent uses preliminary action by preparing the memory cell state before the read operation completes. The control signals are designed to ensure that read operations are fully completed and stable before the next operation begins, eliminating the need for extended pulse widths and reducing time loss
Data Source
AI summary
A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.