Dual-Port Memory Replica Cell Area Reduction
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Solution Overview
Problem
In dual-port memory circuits, the placement of replica cells increases the chip area, making it difficult to mount on a wiring board or chip due to the doubling of the replica memory cell block area and elongation of the memory chip.
Innovation Solution
A dual-port memory circuit configuration with separate replica cell arrays for each access port, where replica bit lines are formed by short-circuiting half-length inversion and non-inversion bit lines, allowing for equivalent transistor placement to memory cells and reducing the area occupied by replica cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replica memory cells are added to each dual port for generating internal timing signals, then the ability to handle process variations is improved, but the chip area increases and mounting becomes difficult
Solution Approach 1:
The patent merges the replica cell blocks for both dual ports into a single shared replica cell block. Instead of having separate replica cells for port 0 and port 1, the invention uses a common replica cell block that can serve both ports, thereby reducing the total chip area while maintaining the ability to generate internal timing signals for both ports independently through separate replica bit lines.
Solution Approach 2:
The shared replica cell block performs multiple functions: it generates internal timing signals for both dual port 0 and dual port 1, and serves as a common reference for both ports' sense amplifier operations. This multi-functional design eliminates the need for separate replica cells for each port, resolving the area contradiction.
2Adaptability or versatility
If separate replica cell blocks are provided for each dual port, then internal timing can be generated for each port, but the memory chip becomes larger and elongated
Solution Approach 1:
The invention combines the replica cell blocks into a single shared structure that serves both dual ports, preventing the chip from becoming larger and elongated. The shared replica cell block is positioned centrally and shares bit lines with both ports, maintaining a compact chip shape while supporting parallel asynchronous read-access.
Solution Approach 2:
The patent reorganizes the spatial arrangement by having the shared replica cell block share bit lines with both dual ports through a common structure, rather than placing separate replica blocks adjacent to each port. This dimensional reorganization maintains compactness while preserving the parallel access capability.
3Measurement precision
If the area of replica memory cell block is doubled for dual ports, then timing accuracy for each port is maintained, but mounting to wiring board or chip is hindered
Solution Approach 1:
The invention merges the replica cell blocks into a shared structure that maintains timing accuracy for both dual ports without doubling the area. The shared replica cell block uses separate replica bit lines (first replica bit line for port 0, second replica bit line for port 1) to generate independent internal timing signals, preserving timing precision while reducing area to facilitate mounting.
Data Source
AI summary
The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.