Dual Port Memory Scan Cell for ATPG Coverage
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Solution Overview
Problem
Current memory macro designs without embedded scan chains on address and control pins face challenges in automatic test pattern generation (ATPG) coverage, leading to increased test time and hardware costs, and existing solutions either prolong runtime or add unnecessary hardware.
Innovation Solution
Implementing a dual port memory with pseudo dual ports and embedded scan control registers, utilizing custom timing pulses and data usage models to create a double pump scan cell design that minimizes latch counts and matches actual timing, while adding a scan enable signal to support full scan coverage on address and control pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If random access memory based sequential ATPG patterns are generated, then ATPG coverage on memory macro pins is improved, but run time for ATPG tool and test time increase
Solution Approach 1:
The patent segments the memory macro testing into two distinct paths: a scan path for structural coverage and a functional path for behavioral coverage. This segmentation allows the scan path to provide rapid structural testing while the functional path handles complex memory operations, thereby reducing overall test time while maintaining comprehensive ATPG coverage.
Solution Approach 2:
The patent introduces scan chains as intermediary structures that connect to address pins, control pins, and data pins of the memory macro. These scan chains act as mediators that enable structural testing of previously inaccessible pins without requiring full functional memory operation, thus reducing test time while improving ATPG coverage.
2Reliability
If observation scan cells are added on drivers of input pins, then ATPG coverage on memory macro pins is improved, but hardware cost increases
Solution Approach 1:
The patent designs scan chains that serve multiple functions: they provide structural testing capability, enable observation of internal signals, and maintain compatibility with functional memory operation. This multi-functionality eliminates the need for separate observation scan cells, reducing hardware cost while maintaining improved ATPG coverage.
Solution Approach 2:
The patent merges the scan chain structures with the existing memory macro I/O interfaces by connecting scan chains to address pins, control pins, and data pins. This merging integrates structural testing capability into the existing functional interface, eliminating the need for additional separate observation hardware and thereby reducing hardware cost.
3Reliability
If embedded scan chains are added to memory macro, then full scan coverage is achieved, but design complexity increases
Solution Approach 1:
The patent extracts the scan chain functionality from the core memory array structure and implements it as separate, modular scan chain units that connect to memory macro pins. This extraction isolates the complexity of scan logic from the memory array design, allowing independent optimization and simplification of each component while achieving full scan coverage.
Data Source
AI summary
Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.