Dual-Port Memory Using Single-Port SRAM and Time-Multiplexed Control
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Solution Overview
Problem
Conventional dual-port random access memory (DPRAM) devices require complex eight-transistor (8T) memory cells, leading to increased circuit area and power consumption due to the large number of memory cells in the array.
Innovation Solution
Implementing a dual-port memory device using a single-port memory device with control circuitry, specifically a six-transistor (6T) static RAM (SRAM) and a clock generator that operates at different clock rates to provide DPRAM functionality, reducing complexity and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional 8T memory cells are used to implement DPRAM, then simultaneous read/write access functionality is achieved, but circuit area and power consumption increase significantly
Solution Approach 1:
The patent segments the dual-port access functionality into time-multiplexed operations. Instead of using complex 8T cells for simultaneous access, the invention uses simpler 6T cells with control circuitry that multiplexes port A and port B access over time, achieving dual-port functionality without requiring both ports to operate simultaneously in the same memory cell.
Solution Approach 2:
The patent introduces control circuitry as an intermediary between the single-port memory array and the dual-port interface. This control logic manages the time-multiplexed access to the memory array, coordinating read and write operations from both ports without requiring complex memory cell structures.
2Adaptability or versatility
If conventional 8T memory cells are used to implement DPRAM, then simultaneous read/write access functionality is achieved, but power consumption increases significantly
Solution Approach 1:
The patent segments the dual-port access functionality into time-multiplexed operations. Instead of using complex 8T cells for simultaneous access, the invention uses simpler 6T cells with control circuitry that multiplexes port A and port B access over time, achieving dual-port functionality without requiring both ports to operate simultaneously in the same memory cell.
Solution Approach 2:
The patent introduces control circuitry as an intermediary between the single-port memory array and the dual-port interface. This control logic manages the time-multiplexed access to the memory array, coordinating read and write operations from both ports without requiring complex memory cell structures.
3Area of stationary object
If 6T memory cells are used with control circuitry, then circuit area and power consumption are reduced, but implementation complexity increases
Solution Approach 1:
The control circuitry is designed to perform multiple functions: it manages time-multiplexed port access, coordinates read/write operations, handles address and data routing, and synchronizes operations between the two ports. By making the control logic universal and multi-functional, the patent reduces the need for separate dedicated circuits for each function.
Data Source
AI summary
An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate.