Dual-Port NVDIMM Hardware Data Replication

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Solution Overview

Problem

Single-port NVDIMMs burden the CPU with time-consuming data migration processes, leading to increased recovery times and trapped data in the event of failures, as they require software-level high-availability models that are not transparent and result in delayed data durability.

Innovation Solution

Dual-port NVDIMMs implement high-availability models on a hardware level, allowing transparent data replication through a second port, enabling the CPU to focus on processing while the NVDIMM manager circuit handles data migration in the background, using universal memory and a DMA engine to move data at hardware speeds between memory application servers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If single-port NVDIMMs are used, then device complexity is reduced, but CPU burden increases and recovery time increases due to time-consuming data migration processes

Engineering Contradiction:

Improvememory module complexityVSAvoidrecovery time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent divides the memory module into two independent ports: a first port for CPU access and a second port for manager circuit access. This segmentation allows simultaneous data operations without CPU involvement in background replication, resolving the contradiction by reducing CPU burden while maintaining data durability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a manager circuit as an intermediary component that handles data replication in the background through the second port. This intermediary performs time-consuming data migration without burdening the CPU, thereby reducing recovery time while keeping the memory module architecture manageable.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If single-port NVDIMMs are used, then device complexity is reduced, but data durability is delayed due to software-level high-availability models

Engineering Contradiction:

Improvememory module complexityVSAvoiddata durability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent replaces software-level high-availability models with a hardware-level implementation. The dual-port architecture with dedicated manager circuit access enables transparent data replication through hardware mechanisms, ensuring data durability is achieved faster and more reliably without software overhead.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The manager circuit autonomously performs data replication and migration tasks in the background without requiring CPU intervention. This self-service capability ensures data durability is maintained continuously, resolving the contradiction by improving reliability while keeping the overall system complexity manageable.

Inventive Principle:

Principle #25Self-service

3Speed

If dual-port NVDIMMs are used, then data replication speed increases through hardware-level operations, but device complexity increases

Engineering Contradiction:

Improvedata replication speedVSAvoidmemory module complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The memory module is segmented into two independent ports with dedicated functions: first port for CPU access and second port for manager circuit access. This segmentation enables parallel data operations that increase replication speed while distributing complexity across separate components rather than concentrating it in a single complex unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The dual-port architecture provides multi-functionality by enabling simultaneous CPU access and background data replication through separate ports. This universal design achieves high-speed data replication while maintaining compatibility with existing CPU architectures, balancing speed improvement with manageable complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Productivity

If dual-port NVDIMMs are used, then CPU burden is reduced by enabling background data migration, but device complexity increases

Engineering Contradiction:

ImproveCPU processing efficiencyVSAvoidmemory module complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

A manager circuit is introduced as an intermediary component that handles background data migration tasks. This intermediary performs time-consuming operations without burdening the CPU, thereby improving CPU processing efficiency while concentrating the added complexity in a dedicated management unit rather than distributing it throughout the system.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The manager circuit autonomously performs data replication and migration in the background without requiring CPU resources. This self-service capability frees the CPU for productive work while isolating the increased device complexity to the self-managing circuit, resolving the contradiction between productivity and complexity.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10157017B2Replicating data using dual-port non-volatile dual in-line memory modules

Publication Date: 2018.12.18 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.