Dual-Port PLD Bus Architecture for Synchronized Multi-Controller Transfer
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Solution Overview
Problem
Conventional bus controller-based programmable logic devices (PLDs) are limited in handling a large number of PLD modules and fail to provide synchronized data and control for multiple motor or digital bus controllers, restricting the number of system triggers they can manage.
Innovation Solution
A dual-port unit is interposed between bus controllers, featuring first and second data transfer layers with write and read areas, and data transfer control units that prevent writes to read areas during reads, enabling simultaneous data transfer and mirroring of data across the layers, supporting up to thirty-one or more PLD modules with synchronized command sequence execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional bus controller-based PLD architecture is used, then the system can manage basic data transfer between bus controllers, but the number of PLD modules that can be handled is limited and synchronized control of multiple bus controllers is not achieved
Solution Approach 1:
The patent divides the data transfer system into multiple independent data transfer layers (first data transfer layer, second data transfer layer, etc.), where each layer handles specific bus controller communications. This segmentation allows the system to scale to support more PLD modules by adding more layers without fundamentally redesigning the entire architecture, thus resolving the contradiction between handling more modules and maintaining manageable complexity.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple data transfer layers above the horizontal bus controller connections. Instead of expanding the system in a single plane, the multi-layer architecture adds depth, allowing simultaneous independent data transfers between different bus controller pairs without interference, thereby increasing the number of manageable PLD modules while controlling complexity.
2Productivity
If multiple bus controllers are interconnected to handle more PLD modules, then the system capacity increases, but data transfer conflicts and loss of synchronicity occur
Solution Approach 1:
By segmenting data transfers into separate layers, the patent ensures that data transfers between different bus controller pairs occur in isolated channels. The first data transfer layer handles transfers for one pair of bus controllers while the second layer handles another pair, eliminating conflicts and maintaining reliability even as system throughput increases with more controllers.
Solution Approach 2:
The patent introduces dual-port units as intermediary components between bus controllers, which act as buffers and coordinators. These intermediaries manage data flow, prevent conflicts, and ensure synchronized operation across multiple controllers, thereby maintaining data transfer reliability while enabling higher system throughput through parallel operations.
3Speed
If data transfer layers allow simultaneous read and write operations, then data transfer speed increases, but data integrity is compromised due to write operations during reads
Solution Approach 1:
The patent segments the data transfer paths into dedicated read pathways and write pathways within each data transfer layer. By separating these operations into distinct channels, the system allows simultaneous read and write operations at different speeds without risk of data corruption, thus maintaining both high data transfer speed and data integrity.
Data Source
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AI summary
A bus controller-based programmable logic device (PLD) architecture is provided and includes a dual-port unit (150) interposed between bus controllers (130, 140). The dual port unit includes first and second data transfer layers (151, 152). The first data transfer layer includes write and read areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the second bus controller. The second data transfer layer includes read and write areas for data transfer between the first and second bus controllers, respectively. A write to the read area is prevented during a read by the first bus controller.