DDR Controller with Dual Port RAM for Data Unit Processing
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Solution Overview
Problem
Current memory switch architectures face inefficiencies in managing high-bandwidth, high-capacity data packets due to the need for multiple memory accesses, large memory requirements for format conversion, and low DDR memory utilization, leading to increased costs and reduced operation rates.
Innovation Solution
A device and method utilizing a DDR controller with dual port random access memory units for read and write requests, allowing for single memory access and on-the-fly processing of data units, which includes storing ingress data, fetching, and processing data units within a DDR memory unit to generate egress data units, while managing variable-sized data units and sharing data bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single frame structure is used in memory switch architecture, then device complexity is reduced, but manufacturing precision deteriorates due to format conversion requirements
Solution Approach 1:
The patent implements a universal frame structure that can accommodate multiple data formats (Ethernet frames, ATM cells, IP packets) without requiring format conversion. The DDR memory controller is designed to handle variable-length data units and different protocol formats through a single unified interface, eliminating the need for separate translation hardware for each protocol type.
Solution Approach 2:
The patent segments incoming data into standardized fixed-size blocks (e.g., 64-byte or 128-byte units) that are stored in the DDR memory. This segmentation approach allows different protocol formats to be normalized into uniform blocks, eliminating format conversion requirements while maintaining the ability to reconstruct original formats during egress.
2Adaptability or versatility
If translation hardware is added for protocol interworking, then adaptability improves, but device complexity increases
Solution Approach 1:
The DDR memory controller is designed as a universal interface that handles multiple protocol types (Ethernet, ATM, IP) through a single unified architecture. The controller supports variable-length data units and can accommodate different frame structures without requiring separate translation hardware for each protocol, thereby maintaining adaptability while minimizing complexity.
Solution Approach 2:
The patent implements dynamic memory allocation and flexible data structure handling that adapts to different protocol requirements on-the-fly. The system can dynamically adjust to various data unit sizes and formats without requiring static translation hardware, achieving protocol versatility through dynamic control rather than fixed structural complexity.
3Manufacturing precision
If multiple memory accesses are performed for protocol processing, then manufacturing precision improves, but productivity deteriorates
Solution Approach 1:
The patent performs preliminary data normalization and blocking during the ingress phase, where incoming data of various formats is converted into standardized fixed-size blocks and stored in DDR memory with uniform addressing. This preliminary action ensures that subsequent egress operations can retrieve data in a single memory access without requiring multiple reads for protocol processing, thereby maintaining accuracy while improving operation rate.
Solution Approach 2:
The system maintains continuous data flow through the DDR memory by implementing seamless ingress and egress operations. Data is continuously normalized into standard blocks during ingress and continuously retrieved during egress without interruption or repeated access cycles, ensuring both processing accuracy and high operation rates through uninterrupted data movement.
4Productivity
If DDR memory utilization is increased, then productivity improves, but device complexity increases
Solution Approach 1:
The patent segments data into fixed-size blocks (e.g., 64-byte or 128-byte units) that uniformly fill DDR memory slots. This segmentation enables efficient memory utilization by eliminating wasted space associated with variable-length protocols, while the uniform block structure simplifies memory management through standardized addressing and allocation, thereby improving productivity without increasing complexity.
Solution Approach 2:
The system changes the fundamental parameter of data representation from variable-length protocol-specific formats to fixed-size standardized blocks. This parameter change maximizes DDR memory utilization by eliminating fragmentation and alignment waste, while simultaneously simplifying memory management through uniform data structures that require less complex allocation and retrieval logic.
Data Source
AI summary
A device and method for storing and processing data units. The method includes: storing, at a read request dual port random access (DPR) memory unit, at least one request to read data from a double data rate (DDR) memory unit; storing, at a write request dual port random access (DPR) memory unit, at least one request to write data to a double data rate (DDR) memory unit; selecting a stored request to be sent to the DDR memory unit; wherein if the selected stored request is a write request, storing an ingress data unit at the DDR memory unit; and retrieving a fetched data unit from the DDR memory unit and processing the fetched data unit to provide an egress data unit; wherein the fetched data unit comprises at least a portion of the ingress data unit.