Dual Port Register Out-of-Band Command Interface
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Solution Overview
Problem
Multiprocessor systems face challenges in efficient intercommunication between processors, particularly in managing shared resources and maintaining reliable message exchange without interfering with existing dataflow, which is often queue-driven and resource-intensive.
Innovation Solution
The implementation of a dual port register and a communication interface like the POWERPC DCR bus allows an external processor to issue out-of-band commands to target processors and receive responses using a dedicated communication path, orthogonal to queuing activities, enabling efficient and interference-free communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If queue-driven communication is used for interprocessor communication, then message exchange can be maintained, but resource usage increases and interference with dataflow occurs
Solution Approach 1:
The patent extracts the command transmission function from the queue-driven communication path and places it in a separate direct path through dual port registers. This allows command messages to be transmitted independently without using the queue infrastructure, thereby reducing resource usage while maintaining message exchange reliability.
Solution Approach 2:
The dual port register acts as an intermediary structure that enables direct communication between processors without requiring queue intermediaries. The register provides a dedicated communication channel that bypasses the queue-driven dataflow, reducing resource contention while maintaining reliable command delivery.
2Reliability
If queue-driven communication is used for interprocessor communication, then message exchange can be maintained, but interference with existing dataflow occurs
Solution Approach 1:
The patent extracts command communication from the shared queue-driven dataflow and creates a separate direct communication path using dual port registers. This extraction eliminates interference with existing dataflow while maintaining reliable message exchange through the dedicated register interface.
Solution Approach 2:
The communication system is segmented into two independent paths: queue-driven dataflow for normal operations and direct register access for command transmission. This segmentation allows command messages to be transmitted without interfering with the existing dataflow, as they traverse separate communication channels.
3Productivity
If dual port register is used for command transmission, then communication efficiency improves, but device complexity increases
Solution Approach 1:
The dual port register structure serves multiple functions: it acts as a command transmission medium, a status indication mechanism (through attention bits), and a response return path. This multi-functionality improves communication efficiency while minimizing the increase in device complexity by consolidating multiple communication functions into a single unified structure.
Solution Approach 2:
The patent merges command transmission, status indication, and response communication into a single dual port register structure. By combining these functions, the system achieves high communication efficiency without proportionally increasing device complexity, as the register serves multiple purposes simultaneously.
Data Source
AI summary
Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.