Dual-Port SRAM Boost System for SNM and WM

The comparator circuit proactively identifies potential conflicts between read and write operations by comparing row addresses before they occur. When a conflict is detected, the boost circuit is activated in advance to adjust voltage levels, ensuring cell current stability is maintained before the actual simultaneous operation begins. This preliminary detection and preparation resolves the contradiction by preventing current instability rather than reacting to it.

The invention dynamically changes voltage parameters (VDD and VSS levels) based on the operational state of the SRAM cell. By detecting simultaneous read/write operations and adjusting the voltage difference accordingly, the system maintains optimal cell current stability while allowing high-speed simultaneous operations. This parameter adjustment resolves the contradiction between operational efficiency and reliability.

The boost circuit operates periodically rather than continuously, activating only when the comparator detects simultaneous read/write operations on the same cell. During normal single-port or non-conflicting dual-port operations, the voltage levels remain at standard values with minimal power consumption. When conflicts are detected, the boost circuit temporarily increases the voltage difference to maintain SNM and WM, then returns to normal operation. This periodic activation resolves the contradiction between reliability and power consumption.

The system uses its own operational status information (row address comparisons) to automatically control the voltage adjustment. The comparator monitors the SRAM's own read/write operations and triggers the boost circuit only when necessary, eliminating the need for external control signals. This self-service mechanism ensures SNM and WM are maintained only when needed, optimizing power consumption while preserving reliability.

The comparator circuit serves as an intermediary between the read/write operations and the boost circuit. It monitors row addresses from both ports and generates control signals for the boost circuit only when conflicts are detected. This intermediary approach simplifies the overall control logic by using a dedicated detection mechanism rather than requiring complex continuous monitoring, resolving the contradiction between reliability and device complexity.

The voltage boosting function is extracted as a separate, independently controlled circuit rather than being integrated into the main SRAM operation logic. The boost circuit is activated only when the comparator detects specific conflict conditions, separating the reliability enhancement function from the normal operational logic. This extraction reduces overall device complexity by allowing the boost functionality to be selectively engaged without affecting the main SRAM control structure.