Dual Port SRAM Cell Transistor Interconnection for Current Distribution
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Solution Overview
Problem
Conventional dual port SRAM cells face issues with current crowding and misalignment between pass-gate and pull-down transistors, leading to uneven current distribution and performance mismatches due to the need for wider pull-down transistors to support parallel operations.
Innovation Solution
The design interconnects sources and drains of pull-down transistors to form a single effective transistor, with a shared gate and separate active regions to ensure even current distribution and reduce the impact of misalignment, using metal lines and conductive features to connect the transistors and maintain uniform channel widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If pull-down transistors are made twice as wide as pass-gate transistors to support parallel operations, then the drive current capability is improved, but manufacturing precision deteriorates due to misalignment and current crowding
Solution Approach 1:
The pull-down transistor is divided into two separate transistors (first pull-down transistor and second pull-down transistor) with separate active regions. Each transistor has its own gate electrode, allowing independent formation and alignment processes. This segmentation eliminates the current crowding effect at intersection regions and prevents mismatching caused by misalignment, while still achieving the required drive current capability through parallel operation of the two transistors.
2Power
If wider pull-down transistors are used to sustain twice the drive current, then current carrying capacity is improved, but device complexity increases due to L-shaped active regions and intersection regions
Solution Approach 1:
The complex L-shaped active region is segmented into two separate rectangular active regions (first active region and second active region). Each active region is simple in geometry and can be formed using standard fabrication processes without creating intersection regions. This segmentation reduces device complexity while maintaining the current carrying capacity through parallel operation of the two pull-down transistors.
Solution Approach 2:
Instead of increasing the width of a single transistor in one dimension (creating L-shaped regions), the solution distributes the current carrying capacity across two separate transistors in the spatial dimension. Each transistor has a standard rectangular active region, and their parallel operation achieves the required total current capacity without geometric complexity.
Data Source
AI summary
An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.