Dual Port SRAM Cell Symmetric Metal Interconnect Layout
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Solution Overview
Problem
Existing dual port static random access memory cells face challenges in enhancing reading speed and bit line coupling due to asymmetric metal interconnect layouts, which result in increased resistance and reduced efficiency.
Innovation Solution
A dual port static random access memory cell with a symmetric metal interconnect layout, where a first power line is positioned between two word lines, and bit lines are placed between the power line and each word line, ensuring symmetric read current distribution and improved bit line coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If an asymmetric metal interconnect layout is used in dual port SRAM, then the layout area can be reduced, but the reading speed decreases and bit line coupling deteriorates
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately uses a symmetric metal interconnect layout where bit lines are positioned symmetrically with respect to power lines and word lines. This symmetry ensures equal electrical path lengths from bit lines to word lines, providing balanced read current distribution across both ports, which improves reading speed and bit line coupling while maintaining compact area through efficient resource sharing
2Area of stationary object
If an asymmetric metal interconnect layout is used in dual port SRAM, then the layout area can be reduced, but the resistance increases
Solution Approach 1:
The patent uses symmetric positioning of bit lines relative to power lines and word lines, ensuring that electrical paths from both bit lines to their respective word lines have equal length and equivalent resistance. This symmetry compensates for the limited layout area by optimizing the electrical characteristics, maintaining low and balanced resistance values that improve signal integrity and reduce voltage drop
3Area of stationary object
If an asymmetric metal interconnect layout is used in dual port SRAM, then the layout area can be reduced, but the bit line coupling deteriorates
Solution Approach 1:
The patent implements symmetric interconnect geometry where bit lines are equidistant from power lines and word lines, creating identical electrical environments for both read ports. This symmetry ensures that read currents are evenly distributed and that bit line coupling capacitances are balanced, improving signal integrity and reducing crosstalk between ports while maintaining compact area through shared power line infrastructure
Data Source
AI summary
A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.