Dual Port SRAM Control Module for Low Voltage Write Margin
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Solution Overview
Problem
Dual port memory devices face functionality and reliability issues due to low operating voltage, exacerbated by transistor variations and reduced physical sizes, which compromise the write margin and concurrent access capabilities.
Innovation Solution
A dual port SRAM design with two access ports (PORT A and PORT B) that includes a control module to manage signal generation for bit lines and word lines, allowing independent and asynchronous access, and a precharge module to equalize bit-line signals during dummy accesses, thereby enhancing write margin and preventing contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the operating voltage of a memory device is reduced to save power, then energy consumption decreases, but functionality and reliability deteriorate due to the operating voltage approaching the threshold voltage of transistors
Solution Approach 1:
The memory device is segmented into multiple independent port modules, each capable of autonomous operation. This segmentation allows the write operation to be isolated and protected from interference by read operations on other ports, maintaining write margin reliability even at low operating voltages where transistor characteristics are more sensitive
Solution Approach 2:
A control module acts as an intermediary between multiple ports and the bit cell array. It manages concurrent access requests, prevents dummy accesses, and coordinates read/write operations to eliminate interference. This intermediary ensures that write operations complete reliably without being disrupted by simultaneous read operations on the same bit cell, addressing the reliability issue at low voltages
2Adaptability or versatility
If dual port bit cells are designed to support independent and asynchronous access, then access versatility improves, but susceptibility to low operating voltage problems increases compared to single port bit cells
Solution Approach 1:
The control module implements feedback mechanisms to monitor the state of bit cells during concurrent operations. When a read operation is detected on one port while a write operation is in progress on another port accessing the same bit cell, the control module provides feedback to prevent the read operation, thereby protecting the write margin and ensuring reliable operation at low voltages
Solution Approach 2:
The control module performs preliminary checks before allowing read operations to proceed. It detects potential conflicts between read and write operations on the same bit cell in advance and prevents the harmful read operation from occurring, thereby proactively protecting against write margin degradation and reliability issues at low operating voltages
Data Source
AI summary
A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.