Dual-Port SRAM Data Inversion Mitigation
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Solution Overview
Problem
Dual-port SRAMs with twisted bit lines suffer from data inversion issues due to capacitive loading disparities between different metal layers used for routing signals, affecting the speed and accuracy of data read and write operations.
Innovation Solution
The implementation of data input and output logic circuitry that drives bit lines and sense amplifiers to ensure proper data writing and reading, utilizing twisted bit lines to mitigate coupling issues and prevent data inversion, including tri-state buffers, multiplexers, and XOR gates to manage control signals and bit line signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If twisted bit lines are used to provide symmetrical balance to the sense amplifier, then the sense amplifier balance is improved, but data inversion issues occur due to capacitive loading disparities
Solution Approach 1:
The patent applies parameter changes by introducing data input logic circuitry that modifies the electrical characteristics of the bit lines. The logic circuitry changes the capacitive loading parameters and signal drive strengths to compensate for the inversion effect, allowing the twisted bit lines to maintain their symmetrical balance benefit while eliminating the data inversion problem through adjusted electrical parameters.
Solution Approach 2:
The patent uses data input logic circuitry as an intermediary between the bit line drivers and the bit lines themselves. This intermediary circuitry manages the capacitive loading disparities and prevents data inversion by conditioning the signals before they reach the twisted bit lines, while allowing the twisted bit lines to maintain their symmetrical structure for sense amplifier balance.
2Adaptability or versatility
If different metal layers are used to route signals in dual port SRAM, then routing flexibility is improved, but capacitive loading disparity occurs affecting word line operating times
Solution Approach 1:
The patent applies parameter changes by introducing logic circuitry that adjusts the electrical characteristics of the bit lines. The circuitry modifies drive strengths, capacitive loading, and signal timing parameters to compensate for the disparities introduced by different metal layer routing, thereby maintaining consistent word line operating times while preserving routing flexibility.
3Reliability
If data input logic circuitry is added to prevent data inversion, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the data input logic circuitry to serve multiple functions: it drives the bit lines, manages capacitive loading, prevents data inversion, and coordinates with the sense amplifiers. By making the logic circuitry multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving high data accuracy.
Data Source
AI summary
A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.