Dual-Port SRAM Array for Single-Cycle Full Adder Logic
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Solution Overview
Problem
Current static random access memory (SRAM) cells cannot perform certain logic functions, such as exclusive OR (XOR), and full adder operations in a single clock cycle, which is desirable for advanced computational tasks like graphics processing units (GPUs) and big data operations.
Innovation Solution
A CMOS implemented memory cell and processing array with dual-port AND cells and 3-port SRAM complementary XOR cells, capable of performing full adder operations in a single clock cycle, by utilizing cross-coupled inverters and access transistors with split bit lines and advanced logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SRAM cells are used for basic Boolean operations, then simple logic functions (AND, OR, NAND, NOR) can be performed, but certain logic functions (such as XOR) cannot be implemented
Solution Approach 1:
The patent implements a dual-port SRAM cell structure where the same physical cell can perform multiple logic functions (AND, OR, NAND, NOR, XOR, and full adder operations) by configuring different word lines and bit line connections. This multi-functional approach allows a single cell type to replace what would otherwise require multiple specialized cell types, achieving versatility without proportionally increasing device complexity.
Solution Approach 2:
The patent uses dynamic control of word lines (WL0, WL1) and bit lines to switch the cell's functionality between different logic operations. By dynamically activating different ports and connection configurations during operation, the cell can adapt its behavior to perform various logic functions including the previously unimplementable XOR operation, resolving the contradiction between versatility and complexity.
2Productivity
If full adder operations are performed using conventional methods, then multiple clock cycles (4 cycles) are required, but this reduces computational speed for applications like GPU and big data processing
Solution Approach 1:
The patent pre-configures the dual-port SRAM cell with complementary XOR cells and appropriate word line/bit line connections during the design stage, so that when a full adder operation is initiated, all necessary logic paths are already in place. This preliminary configuration eliminates the need for multiple sequential clock cycles required by conventional full adder implementations, enabling the operation to complete in a single clock cycle and significantly improving productivity for computational applications.
Solution Approach 2:
The patent combines multiple logic functions (XOR operations, AND operations, and carry logic) into a single integrated cell structure that operates simultaneously. By merging these separate logic stages that would traditionally require sequential execution across multiple clock cycles into one unified structure, the full adder operation completes in a single clock cycle, resolving the time loss issue while maintaining high computational speed.
3Productivity
If more cells are activated to perform computations, then computational capability increases, but power consumption increases proportionally
Solution Approach 1:
The patent enables selective activation of specific cell ports and logic paths based on the required computation. Rather than activating all cells uniformly, the dual-port structure allows precise control over which cells participate in which logic operations, enabling computational capability to be scaled locally without proportionally increasing power consumption across the entire array. This resolves the contradiction by allowing targeted computational power usage.
Data Source
AI summary
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.