Dual-Port SRAM Cell Layout for Simpler Routing and Latch-Up Immunity
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Solution Overview
Problem
Existing dual-port SRAM cells face challenges in routing arrangement and lithography process windows due to complex metal routing, which affects their performance and efficiency in deep sub-micron integrated circuit technology.
Innovation Solution
The design of a 10T SRAM cell with specific configurations of transistors and metal layer arrangements, including the use of long contacts and gate vias, to simplify routing and increase spacing between n-type and p-type devices, reducing latch-up and soft-error-rate while improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex metal routing is used in dual-port SRAM cells, then parallel operation capability and bandwidth are improved, but routing arrangement complexity and lithography process window challenges increase
Solution Approach 1:
The patent divides the metal routing into multiple layers (first metal layer for word lines, second metal layer for bit lines). This segmentation allows each layer to handle specific routing functions independently, reducing the complexity of any single layer while maintaining the overall parallel operation capability and bandwidth of the dual-port SRAM cell.
2Productivity
If feature size is decreased to increase packing density, then functional density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes multiple metal layers to route signals in three-dimensional space rather than confined to a single plane. This dimensional transition allows for higher packing density and functional density without proportionally increasing manufacturing complexity, as each layer can be processed using standard lithography techniques optimized for its specific routing requirements.
Data Source
AI summary
The static random access memory (SRAM) cell of the present disclosure includes a first pull-down device, a second pull-down device, a first pass-gate device, and a second pass-gate device in a first p-well on a substrate; a third pull-down device, a fourth pull-down device, a third pass-gate device, and a fourth pass-gate device in a second p-well on the substrate; a first pull-up device and a second pull-up device in an n-well between the first p-well and the second p-well; and a first landing pad between the second pull-down device and the first pull-up device. The first landing pad is electrically coupled to a gate structure of the second pass-gate device by way of a first gate via.