Dual-Port 8T SRAM Layout for Lower Resistance and Higher Density
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Solution Overview
Problem
In the nanometer era, dual-port SRAM cells face challenges such as increased area, higher metal coupling capacitance, and reduced differential speed due to bit-line and Vss conductor resistance issues, which complicate BEOL metal routing and impact cell speed and V_min performance.
Innovation Solution
The implementation of two abutting dual-port 8T-SRAM cells with n+1 WWL landing lines and n+1 Vdd lines, utilizing multi-gate semiconductor devices like FinFETs, to improve cell scaling and density, and reduce metal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional dual-port SRAM cell layout is used, then cell area increases, but metal coupling capacitance and resistance increase causing reduced differential speed
Solution Approach 1:
The patent transitions from planar 2D layout to three-dimensional vertically-stacked architecture, where bit-lines are routed in different vertical layers (first bit-line in first metallization layer, second bit-line in second metallization layer). This dimensional separation reduces metal coupling capacitance and resistance while maintaining compact cell area, directly resolving the contradiction between area and speed.
Solution Approach 2:
The SRAM cell is divided into multiple vertical layers with distinct functions: storage transistors in lower layers, bit-line routing in intermediate layers, and read/write port control in upper layers. This segmentation allows optimized routing paths for each signal type, reducing interference and improving differential speed without increasing overall cell area.
2Reliability
If more metal routing layers are added to reduce resistance, then BEOL metal routing complexity increases
Solution Approach 1:
The vertically-stacked architecture uses a standardized multi-layer metallization structure that serves multiple functions: power delivery, signal routing, and heat dissipation. The same vertical stacking approach is applied uniformly across all SRAM cells in the array, providing a universal solution that reduces resistance without requiring cell-specific complex routing, thus managing BEOL complexity.
3Area of moving object
If cell scaling is pursued to increase density, then area decreases but metal resistance and coupling capacitance increase
Solution Approach 1:
By moving critical signal routing to vertical dimensions with multiple metallization layers, the patent achieves effective 3D scaling. This allows planar cell area to be reduced for higher density while vertical routing paths maintain shorter effective lengths and lower resistance, preventing the typical scaling-induced resistance increase.
Solution Approach 2:
The patent implements nested vertical stacking where storage cells are positioned in lower layers, with read/write port circuitry and bit-line routing nested in upper layers. This nested architecture allows continuous scaling of cell area while maintaining electrical performance through the vertical nesting of functional blocks.
Data Source
AI summary
A memory device includes a first SRAM cell, a second SRAM cell, a write word line (WWL) landing line, and a Vdd line. The first SRAM cell and the second SRAM cell respectively include 8 transistors. The first WWL landing line is disposed inside a cell boundary of the first SRAM cell. The Vdd line is disposed in a cell boundary of the second SRAM cell. The first WWL landing line and the Vdd line are in a same layer.