Dual-Port SRAM Read-Write Timing Control for Disturb Prevention
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Solution Overview
Problem
Dual-port SRAM cells experience 'disturb' errors and collisions between write and read operations when multiple ports access the same memory cells, degrading data accuracy and increasing the lower bound operating voltage.
Innovation Solution
The semiconductor device activates the read word line before the write word line in an operation cycle that performs both read and write operations, ensuring read data accuracy and alleviating address limitations on simultaneous access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ports access the same memory cells simultaneously, then productivity is improved, but disturb errors and collisions occur degrading data accuracy
Solution Approach 1:
The patent applies preliminary action by activating the read word line before the write word line in the same operation cycle. This sequencing ensures that the read operation completes before the write operation begins, preventing write disturb to the read data and avoiding collisions, thus maintaining data accuracy while enabling simultaneous access from multiple ports
2Productivity
If read and write operations are performed on the same memory cell in the same operation cycle, then productivity is improved, but the lower bound operating voltage increases
Solution Approach 1:
The patent sequences operations by performing the read operation first (activating read word line) before the write operation (activating write word line). This preliminary execution of the read operation allows the memory cell to complete its read cycle before undergoing write, reducing the voltage stress on the memory cell while maintaining high operation efficiency
Data Source
AI summary
A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.