Dual Port SRAM Cell Segmentation for Signal Stability
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Solution Overview
Problem
Standard 6T SRAM cells face limitations in read and write cycles due to the need for strong bit line pull-up transistors, leading to instability and difficulty in sensing data, especially when multiple cells are active, and require strong write drivers, which is undesirable.
Innovation Solution
A dual port SRAM cell design with cross-coupled inverters and isolation circuits that allow for independent operation of read and write ports, eliminating the need for a static pull-up transistor and enabling more cells to be turned on without signal degradation, thus improving sensing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard 6T SRAM cells use strong bit line pull-up transistors to enable multiple cells to be active, then more cells can be turned on, but signal stability deteriorates and sensing becomes difficult
Solution Approach 1:
The patent segments the SRAM cell structure into distinct read and write ports with separate access transistor pairs. Each port has its own access transistors (first and second access transistors for read port, third and fourth access transistors for write port), allowing independent operation. This segmentation enables the read port to function without requiring strong pull-up transistors, as the isolated read access transistors can operate effectively with weaker drive strength, thus maintaining signal stability while allowing multiple cells to remain active.
2Ease of operation
If standard 6T SRAM cells require strong write drivers to perform write operations, then write capability is achieved, but power consumption increases
Solution Approach 1:
The patent divides the access transistor functionality into separate read and write port access transistor pairs. The write port uses dedicated third and fourth access transistors that are controlled independently from the read port transistors. This segmentation allows the write operation to use only the necessary write port transistors and associated write bit lines, rather than requiring all access transistors to be strongly driven, thereby reducing overall power consumption while maintaining write capability.
Solution Approach 2:
The patent implements dynamic control of access transistor gates through separate word lines (first and second word lines for read port, third and fourth word lines for write port). This dynamic gating allows the write port to activate only when needed, and the isolated write access transistors can be optimally sized and driven for write operations without continuously consuming power. The dynamic operation enables write capability on demand while minimizing power consumption during idle or read-only periods.
3Reliability
If standard 6T SRAM cells use cross-coupled inverters for data storage, then data retention is achieved, but read and write operations interfere with each other
Solution Approach 1:
The patent segments the access transistor control into separate read and write ports, each with its own access transistor pairs and controlling word lines. The read port uses first and second access transistors controlled by first and second word lines, while the write port uses third and fourth access transistors controlled by third and fourth word lines. This segmentation allows simultaneous or independent activation of read and write operations on the same SRAM cell without interference, as each port has dedicated control pathways. The cross-coupled inverters maintain data retention while the segmented access transistors prevent operational interference.
Data Source
AI summary
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.