Dual-Port SRAM Cell Segmented Pull-Down Devices
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Solution Overview
Problem
Dual-port SRAM cell structures face challenges such as data node leakage, device matching issues, and current crowding due to increased pull-down drive capability requirements, which complicate the lithography process and affect performance in deep sub-micron integrated circuit technology.
Innovation Solution
The proposed SRAM cell design includes a dual-port structure with cross-coupled inverters, multiple parallel pull-down devices, and pass-gate devices, along with specific metal routing configurations that improve device layout and reduce noise shielding, allowing for better lithography patterning and uniform density in metal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the pull-down device width is doubled to provide sufficient drive capability for dual-port operation, then the pull-down drive capability is improved, but the layout becomes L-shaped or T-shaped causing data node leakage and current crowding
Solution Approach 1:
The pull-down device is segmented into multiple smaller devices (first pull-down device and second pull-down device) that are distributed across different active regions. This segmentation maintains the required total drive capability while avoiding the L-shaped or T-shaped layout problems associated with a single large pull-down device.
Solution Approach 2:
Different active regions are assigned specific functions: first active regions contain first pull-down devices, second active regions contain second pull-down devices, third active regions contain first pass-gate devices, and fourth active regions contain second pass-gate devices. This local specialization optimizes performance while avoiding current crowding.
2Quantity of substance
If the feature size is decreased to increase packing density, then the packing density is improved, but the lithography process becomes more difficult and performance degrades
Solution Approach 1:
The cell structure uses asymmetric arrangement of active regions and devices, with specific regions dedicated to specific functions. This asymmetric design, combined with straight line shapes, simplifies lithography patterning while maintaining high packing density in deep sub-micron technologies.
Solution Approach 2:
The patent distributes devices across multiple active regions in a systematic arrangement, effectively utilizing spatial dimensions to achieve high density while maintaining manufacturability through regular, lithography-friendly patterns.
3Reliability
If multiple parallel pull-down devices are distributed in different active regions, then the current crowding issue is reduced, but the device layout complexity increases
Solution Approach 1:
The cell structure uses universal building blocks (inverters with pull-down and pass-gate devices) that are replicated and distributed across different active regions. This modular approach reduces current crowding while maintaining layout regularity and reducing overall complexity.
Data Source
AI summary
The present disclosure provides a static random access memory (SRAM) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction. The fins include source, drain, and channel regions for various pull-up, pull-down, and pass-gate fin field-effect transistors (FinFETs). The SRAM cell further includes various gate features over the fins and extending lengthwise generally along the first direction. The gate features include gate regions for the various FinFETs.