Dual Port SRAM Cell Layout Using Three-Column Segmentation
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Solution Overview
Problem
Dual port SRAM cells have increased size and parasitic capacitance due to additional switches, affecting memory circuit performance by limiting word line width and increasing resistance.
Innovation Solution
A three-column configuration for dual port SRAM cells, with cross-coupled inverters and strategically positioned switches, reduces word line length and widens spacing to manage parasitic resistance and capacitance effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual port SRAM cells use additional switches to enable simultaneous reading by two circuits, then reading functionality is improved, but cell size and parasitic capacitance increase
Solution Approach 1:
The patent segments the SRAM cell into distinct functional columns: a first column containing switches for a first port, a second column containing switches for a second port, and a third column containing cross-coupled inverters. This segmentation allows each column to be optimized independently for its specific function while managing overall cell layout and parasitic effects.
Solution Approach 2:
The patent introduces a third column with cross-coupled inverters that operates in a different dimensional arrangement from traditional two-column SRAM cells. This three-column configuration enables simultaneous dual-port reading by routing word lines through different spatial paths, adding a dimensional approach to conflict resolution.
2Adaptability or versatility
If dual port SRAM cells include additional switches and word lines, then dual port functionality is achieved, but parasitic resistance of word lines increases
Solution Approach 1:
The patent applies different layout strategies to different regions of the cell. The first and second columns are positioned to minimize word line length for their respective ports, while the third column with cross-coupled inverters is strategically placed to reduce overall parasitic capacitance and resistance effects on the word lines.
Solution Approach 2:
By adding a third column dimension with cross-coupled inverters, the patent creates alternative current paths and reduces the effective length of word lines in the first and second columns, thereby reducing parasitic resistance and capacitance while maintaining dual port functionality.
3Area of stationary object
If word line width is reduced to fit additional switches, then cell density is improved, but parasitic resistance increases
Solution Approach 1:
The patent segments the word line routing into distinct paths through the first, second, and third columns. This segmentation allows each column to have optimized width and spacing, preventing the need to reduce overall word line width to accommodate additional switches while maintaining high cell density.
Solution Approach 2:
The three-column configuration adds a spatial dimension that allows word lines to be routed more efficiently. By distributing switches across three columns rather than compressing them into two, the patent maintains adequate word line width and spacing, reducing parasitic resistance while achieving higher cell density.
Data Source
AI summary
A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line.