Dual-Port SRAM Timing Control Circuit for Power Reduction
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Solution Overview
Problem
Dual-port SRAMs face high operational power consumption due to the duration of the wordline being at a high level during read operations, which affects read reliability when bit line voltage differences become insufficient.
Innovation Solution
A dual-port SRAM timing control circuit is designed with NMOS transistors connected between bit lines and ground, using pulse signals and address comparators to dynamically adjust the clock pulse width and discharge speed of bit lines, reducing operational power consumption while maintaining reliable read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wordline is kept at a high level for a longer duration to ensure sufficient bit line voltage difference for reliable reading, then read reliability is improved, but operational power consumption increases
Solution Approach 1:
The patent applies dynamics by making the bit line discharge speed adjustable rather than fixed. A control signal dynamically adjusts the discharge speed of the bit line based on operational conditions, allowing the system to optimize between power consumption and read reliability in real-time. This is achieved through a controllable discharge path that can modulate the discharge rate.
Solution Approach 2:
The patent changes the discharge speed parameter of the bit line to resolve the contradiction. By adjusting the discharge speed, the system can shorten the required wordline high level duration, thereby reducing power consumption while maintaining sufficient voltage difference for reliable reading. The discharge speed is modified through control signals that affect the discharge path characteristics.
2Use of energy by moving object
If the discharge speed of the bit line is increased to shorten the wordline high level duration and reduce power consumption, then operational power consumption is reduced, but bit line voltage difference may become insufficient affecting read reliability
Solution Approach 1:
The patent implements feedback by using the detection of bit line discharge completion to control the discharge process. When the bit line discharge is detected to be completed, the control signal adjusts the discharge path to stop or reduce discharge, preventing over-discharge that would compromise voltage difference. This feedback mechanism ensures that the discharge speed is optimized without sacrificing read reliability.
Solution Approach 2:
The system performs self-service by automatically adjusting the discharge speed based on the operational state. The control circuit monitors the discharge progress and autonomously modifies the discharge path characteristics to maintain optimal performance, eliminating the need for external intervention to balance power consumption and reliability.
3Device complexity
If the discharge path is simplified to reduce circuit complexity, then device complexity is reduced, but control precision over discharge speed is compromised
Solution Approach 1:
The patent applies universality by designing a discharge path control mechanism that serves multiple functions. The same control circuitry that manages the discharge path also provides timing control and adjusts discharge speed, eliminating the need for separate complex control circuits. This multi-functional approach reduces overall device complexity while maintaining control precision.
Solution Approach 2:
The patent merges the discharge path control function with the existing timing control circuitry. By combining these functions into a unified control mechanism, the patent reduces the number of separate components and interconnections, thereby simplifying the overall circuit while preserving the ability to precisely control discharge speed through the integrated control signal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces operational power consumption by shortening the duration of the wordline high level and ensuring sufficient bit line voltage differences, thereby enhancing read reliability and adaptability to asynchronous dual-port clocks.
Implementation Method 1
A first NMOS transistor, a second NMOS transistor and a third NMOS transistor are connected in series between ground and a node of the first bit line to which each SRAM cell structures correspond
Data Source
AI summary
A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the NMOS transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively. The each pulse signals are formed by a corresponding clock signal inputted into a first pulse generator, respectively. An address signal, after passing through an address latch, is inputted into an address comparator for comparison, with the address comparison result outputted to a timing control signal generator; and the pulse signal, after undergoing an AND operation, is inputted into the timing control signal generator, with a timing control signal outputted. When the two address signals are the same, the address comparison result is 1; when the two address signals are not the same, the address comparison result is 0; when the AND result of the two pulse signals is 0, the timing control signal is 1; when the AND result of the two pulse signals is 1, the timing control signal is an inverting signal of the address comparison result. The present invention can reduce the operational power consumption of SRAM without affecting the read reliability.