Dual Port Vertical Transistor Memory Cell Stability
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Solution Overview
Problem
Current dual port SRAM memory cells face challenges in maintaining stability and durability due to variations in potential on charge storage nodes, which affect the ability to unambiguously hold memory states, especially during frequent read/write cycles.
Innovation Solution
A dual port vertical transistor memory cell design featuring merged doped source/drain regions and conductive gate structures around channel regions, with L-shaped gate structures for enhanced coupling and stability, allowing for concurrent read operations and improved charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional horizontal transistor structures are used in dual port SRAM memory cells, then the device can be manufactured using standard processes, but the stability and durability deteriorate due to variations in potential on charge storage nodes during frequent read/write cycles
Solution Approach 1:
The patent transitions from conventional horizontal planar transistor structures to vertical transistor structures, effectively moving the device architecture to another spatial dimension. This vertical configuration allows for better charge confinement and reduced leakage paths, thereby improving potential margin stability on charge storage nodes during frequent read/write cycles while maintaining compatibility with standard manufacturing processes.
Solution Approach 2:
The patent merges the source and drain regions into a single continuous doped region beneath the channel, eliminating the need for separate source and drain structures. This merging reduces the number of interfaces and potential leakage paths, improving the stability of charge storage nodes while simplifying the device structure for manufacturing.
2Adaptability or versatility
If more transistors and interconnect structures are added to improve memory cell functionality, then the device complexity increases, but manufacturing precision and stability deteriorate
Solution Approach 1:
The patent merges multiple transistor functions into the vertical transistor structure, where a single vertical device can perform functions that traditionally required multiple horizontal transistors. The merged source/drain region serves multiple transistors simultaneously, reducing the total number of discrete components while maintaining concurrent read operations capability.
Solution Approach 2:
The vertical transistor structure is designed to be multi-functional, serving as both a storage element and a switching element. The shared doped source/drain region acts as a common electrode for multiple gates, enabling the structure to perform multiple functions with a single component, thereby reducing overall device complexity.
Data Source
AI summary
A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node. A second S/D region includes a second P-type region, a second N-type region, and a second conductive layer thereon to define a second cell node. A PDL transistor and PGLA, PGLB transistors have bottom SD regions in the first N-type region. A PUL transistor has a bottom SD region positioned in the first P-type region. A PDR transistor and PGRA, PGRB have bottom SD regions in the second N-type region. A PUR transistor has a bottom SD region in the second P-type region. A first gate is positioned around channel regions of the PUL and PDL transistors and conductively coupled to the second node. A second gate is positioned around channel regions of the PUR and PDR transistors and conductively coupled to the first node.