Dual Power Rail Structure for Advanced Node Current Density
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Solution Overview
Problem
As semiconductor devices shrink in size, the high current density in power rails leads to reliability concerns such as electro-migration and IR issues due to increased resistance in smaller metal interconnect wires, particularly in emerging technology nodes like 14 nm, 10 nm, 7 nm, and 5 nm.
Innovation Solution
A dual power rail structure is implemented, where a first metal interconnect layer has a lower metal wire, a second layer comprises connection pins coupled to the lower wire via a via layer, and a third layer includes an upper metal wire coupled to the connection pins via another via layer, reducing current density by distributing power across multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor device components are reduced in size to achieve higher integration density, then the number of devices per chip increases, but the current density in power rails increases leading to electro-migration and IR issues
Solution Approach 1:
The patent transitions from a planar single-layer power rail structure to a three-dimensional multi-layer power distribution network. By stacking multiple metal interconnect layers vertically, the power delivery system utilizes the vertical dimension to increase the effective cross-sectional area for current flow, thereby reducing current density and associated reliability issues while maintaining high device integration density.
Solution Approach 2:
The patent divides the power distribution system into multiple discrete metal interconnect layers (first, second, and third metal layers) rather than relying on a single continuous power rail. This segmentation allows current to be distributed through multiple parallel paths, reducing the burden on any single power rail and mitigating electro-migration and IR drop problems.
2Length of moving object
If metal interconnect wire size is reduced to support smaller technology nodes, then device scaling is achieved, but resistance increases causing IR issues
Solution Approach 1:
The patent compensates for reduced wire dimensions by adding vertical stacking of multiple metal layers. This dimensional transition effectively increases the total conductive cross-section available for current flow, offsetting the increased resistance that would result from smaller lateral wire dimensions in advanced technology nodes.
Solution Approach 2:
The patent combines multiple metal interconnect layers into an integrated power distribution system where the first, second, and third metal layers work together to deliver power. This merging of multiple conductive paths creates a composite power delivery system with lower effective resistance than any single layer could provide alone.
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.