Dual-Power Data Retention Latch for Low-Leakage Power-Down

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Solution Overview

Problem

Existing electronic circuits face challenges in efficiently retaining data bits during power down modes to conserve energy and prolong battery life, as current methods lack flexibility in power supply voltage levels.

Innovation Solution

A data retention circuit is designed with a master latch, slave latch, and retention latch operating in different power domains, utilizing a second power supply voltage level independent of the first, allowing for data retention during power down periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data bits are saved using latch circuits during power down events, then data continuity is maintained, but power consumption increases and battery life is reduced

Engineering Contradiction:

Improvedata continuityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The circuit is divided into two independent power domains: a first power domain for normal circuit operation and a second power domain specifically for data retention. This segmentation allows the retention latch to operate independently on a separate power supply (VDD2) that remains active only when data retention is needed, while the main circuit can be fully powered down, thereby minimizing overall power consumption while maintaining data continuity.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If a single power supply voltage level is used for all circuit operations, then circuit design is simplified, but flexibility in power management and leakage current reduction is limited

Engineering Contradiction:

Improvecircuit designVSAvoidpower management flexibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent introduces a vertical dimension of power management by implementing multiple power supply voltage levels (VDD1 for main circuit, VDD2 for retention latch). This dimensional approach to power management enables independent control of power states for different circuit functions, providing enhanced flexibility in power management and the ability to optimize leakage current without significantly complicating the overall circuit design through systematic integration of level shifters and dual power domain architecture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Use of energy by moving object

If the main circuit is powered down to conserve energy, then power consumption decreases, but data bits are lost unless retention mechanisms are implemented

Engineering Contradiction:

Improvepower consumptionVSAvoiddata loss

Core Design Contradiction:

Use of energy by moving objectVSLoss of information

Solution Approach 1:

The retention latch is configured to capture and hold data bits from the main circuit before the power down event occurs. By performing this data capture action in advance, the system ensures that data is securely stored in the retention domain before the main circuit loses power, preventing any data loss while enabling complete power down of the main circuit for maximum energy conservation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250192758A1Data retention circuit and method

Publication Date: 2025.06.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A data retention circuit includes a flip-flop circuit including a master latch coupled to a slave latch, wherein the slave latch includes a first input terminal and a first output terminal, and a series combination of a retention latch and a level shifter coupled between the first input terminal and the first output terminal. The slave latch is configured to be selectively coupled to the series combination through a first transmission gate responsive to a restore signal.