Dual Power Supply Digital Device Input Buffer Voltage Translator
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Solution Overview
Problem
In dual power supply digital devices, the unpredictable application of input/output (I/O) buffer voltage (VDDQ) relative to the core voltage (VDD) can lead to spurious commands or sequences during power on, especially when VDDQ is applied after VDD, causing unpredictable information conveyance to the core due to floating logic levels.
Innovation Solution
A dual power supply digital device design that includes a down converter for generating a regulated core supply voltage and a second supply voltage for I/O buffers, with a p-channel transistor added to the input interfacing circuitry to ensure a stable logic state by coupling the input node to the core supply voltage, allowing non-simultaneous application of VDDQ and VDD without spurious consequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If VDDQ is applied after VDD, then the device can be powered in a specific sequence, but the logic level at the input node becomes unpredictable (floating)
Solution Approach 1:
The patent applies preliminary action by pre-configuring the input interfacing circuitry with a voltage translator latch stage and associated transistors that automatically establish a known logic state at the input node before any external signals are processed. This preliminary circuit configuration ensures that regardless of the power supply sequence, the input node is already in a defined state when VDDQ is applied, preventing floating conditions and spurious commands.
2Adaptability or versatility
If VDDQ is applied with delay relative to VDD, then non-simultaneous powering is possible, but spurious commands or sequences may occur during power on
Solution Approach 1:
The patent applies preliminary anti-action by designing the input interfacing circuitry to preemptively counteract the potential harmful effect of floating logic levels. The voltage translator latch stage, controlled by the second transistor and third transistor, is configured to maintain the input node at a known logic state (either high or low) during the entire power-on transition period, including the delay period when VDDQ is applied after VDD. This preliminary protective configuration prevents spurious commands from occurring in the first place.
3Device complexity
If the input node is left floating during power on, then circuit simplicity is maintained, but unpredictable information conveyance to the core occurs
Solution Approach 1:
The patent applies the intermediary principle by introducing a voltage translator latch stage as a mediating circuit between the external input pad and the core logic. This intermediary circuit, comprising the second transistor, third transistor, and associated capacitors, translates and stabilizes the input signal during power-on transitions. It acts as a buffer that ensures reliable information conveyance to the core by maintaining a known logic state at the input node, preventing direct exposure of the core to floating or unpredictable voltage levels.
Data Source
AI summary
A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.