Dual Precharge Circuit for Nonvolatile Memory Bit Line Control
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Solution Overview
Problem
High integration in semiconductor memory devices leads to reliability issues and slower operating speeds, necessitating improvements in both reliability and speed for nonvolatile memory devices used in storage and host devices.
Innovation Solution
A nonvolatile memory device design featuring a memory cell array with ground selection and string selection transistors, a row decoder circuit, and a page buffer circuit that applies specific voltages to bit lines during precharge operations to enhance data loading and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high integration is implemented in nonvolatile memory devices, then production cost is reduced, but reliability deteriorates due to data damage
Solution Approach 1:
The patent applies preliminary action by performing a first precharge operation on bit lines before data loading occurs. This precharge operation prepares the bit lines in advance by setting them to a predetermined voltage level, ensuring they are ready to receive data without interference from residual charges or voltage fluctuations. This preliminary preparation enhances data integrity during the writing process while maintaining the high integration structure.
Solution Approach 2:
The patent implements preliminary anti-action by applying a second precharge operation after data loading to counteract any potential data corruption or voltage instability. This second precharge operation restores bit lines to a known good state, preventing data damage that could occur during subsequent operations. This dual precharge approach (before and after data loading) proactively prevents reliability issues in high-density memory structures.
2Area of stationary object
If high integration is implemented in nonvolatile memory devices, then device scale is reduced, but operating speed deteriorates
Solution Approach 1:
The first precharge operation prepares bit lines in advance by setting them to a predetermined voltage level before data loading begins. This preliminary preparation eliminates delays that would occur if bit lines needed to be charged during the data writing process, thereby maintaining high operating speed despite the reduced device scale characteristic of high integration.
Solution Approach 2:
The patent maintains continuity of useful action by overlapping the first precharge operation with the data loading process. While bit lines are being precharged to the predetermined voltage level, data is simultaneously loaded into the memory cells. This continuous operation prevents idle time and maintains high operating speed, allowing the compact high-integration device to achieve fast performance.
3Device complexity
If traditional single precharge circuit is used, then device complexity is low, but data loading efficiency deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the precharge function into two distinct precharge circuits: a first precharge circuit that operates before data loading to set bit lines to a predetermined voltage level, and a second precharge circuit that operates after data loading to restore bit lines. This segmentation of the precharge function into separate operational phases improves data loading efficiency by ensuring proper voltage conditions during each stage of the writing process.
Solution Approach 2:
The first precharge circuit performs preliminary action by preparing bit lines in advance before data loading occurs. This precharge operation sets bit lines to the correct voltage level, ensuring they are ready to accurately receive and store data. This preliminary preparation significantly improves data loading efficiency by preventing errors and reoperations that would reduce productivity.
Data Source
AI summary
A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.