Dual Processor System Using DPRAM for Efficient Data Exchange
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Solution Overview
Problem
Dual processor systems face reduced data processing rates and resource utilization due to numerous data transmission operations required for cooperative data processing between processors, leading to inefficiencies in system performance.
Innovation Solution
A dual processor system design that utilizes a dual-ported random access memory (DPRAM) with a configuration area and reduced interrupt pins, allowing for shared data processing work between processors with fewer data transmission operations and hardware requirements, enabling efficient communication and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual processors communicate through DPRAM with multiple mailboxes and interrupt pins, then cooperative data processing capability is improved, but data processing rate decreases and system resources are occupied
Solution Approach 1:
The patent extracts and eliminates redundant components from the DPRAM structure. Specifically, it removes the need for multiple mailboxes and interrupt pins by implementing a simplified communication protocol where processors can directly access each other's memory spaces without requiring separate interrupt notification mechanisms, thereby reducing hardware overhead and improving processing speed
Solution Approach 2:
The patent makes the DPRAM structure more universal by enabling processors to use the same data area for both data storage and interrupt notification purposes. The simplified design allows the data area to serve multiple functions: storing data to be processed, indicating processing status, and enabling inter-processor communication without requiring dedicated separate structures for each function
2Adaptability or versatility
If dual processors perform many data transmission operations for cooperative processing, then task distribution capability is improved, but system resources are occupied and processing efficiency decreases
Solution Approach 1:
The patent merges the data transmission and status notification functions into a single integrated operation. By allowing processors to directly access and modify shared memory areas without requiring separate interrupt signal transmissions, the system combines what were previously separate communication steps into unified memory access operations, reducing overall complexity
3Reliability
If DPRAM uses multiple mailboxes and interrupt pins for processor communication, then communication reliability is improved, but hardware complexity increases
Solution Approach 1:
The patent extracts and removes redundant hardware components including separate interrupt pins and multiple dedicated mailboxes. The simplified design relies on direct memory space sharing between processors, eliminating the need for complex interrupt notification hardware while maintaining communication reliability through software-managed status flags in the shared data area
Solution Approach 2:
The patent creates a universal communication interface where the same data area serves multiple communication purposes. Processors can write data, indicate availability, and signal completion all through the same memory space, eliminating the need for separate dedicated structures for each communication function and thereby reducing hardware complexity
Data Source
AI summary
A dual processor system comprises a first processor, a second processor, and a dual-ported random access memory (DPRAM). When the first processor stores data to be processed by the second processor to the DPRAM and writes interrupt data to the DPRAM, the DPRAM generates a first information status. The second processor reads the interrupt data once when detecting the first information status, processes the to be processed data when successfully reading the interrupt data once, and reads the interrupt data twice when completing processing the to be processed data. The DPRAM generates a second information status when the second processor successfully reads the interrupt data twice, and the first processor identifies that the second processor has processed the to be processed data when detecting the second information status.