Dual Processor Emulation Segmentation for Interpreter Compatibility
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Solution Overview
Problem
Current information processing devices face challenges in achieving high performance and compatibility for interpreter method emulation, as they require high-speed processors that are costly or consume excessive power, and struggle with timing control and memory capacity, especially when dealing with self-modifying code.
Innovation Solution
An information processing device comprising a first processor that directs and a second processor, where the second processor determines whether to execute instructions and notifies the first processor if execution is not possible, allowing both processors to execute processing together, thereby enabling interpreter method emulation with performance suitable for compile method emulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interpreter method is used for emulation, then compatibility and timing control are improved, but processing speed deteriorates
Solution Approach 1:
The emulation processing is segmented into two parts: the first processor executes interpreter method emulation to ensure compatibility and timing control, while the second processor executes compile method emulation to provide high-speed processing. This segmentation allows each processor to specialize in different emulation methods, resolving the contradiction between compatibility and speed.
2Productivity
If high-speed processors are used to improve interpreter method emulation performance, then processing speed is improved, but cost and power consumption increase
Solution Approach 1:
The system segments the emulation workload between two processors with different performance characteristics. The first processor handles compatibility-critical tasks using the interpreter method, while the second processor handles performance-critical tasks using the compile method. This allows the system to achieve high overall performance without requiring both processors to be high-speed, thus reducing power consumption and cost.
3Productivity
If the compile method is used for emulation, then processing speed is improved, but memory capacity requirements increase and timing control becomes difficult
Solution Approach 1:
The system divides the emulation tasks between two processors: the first processor uses the interpreter method which requires less memory but provides better timing control, while the second processor uses the compile method which requires more memory but provides higher processing speed. By segmenting the workload, the system achieves high performance without requiring the full memory capacity to be allocated for all tasks.
Data Source
AI summary
An information processing device is provided for realizing the interpreter method emulation by using a processor having a performance requested for the compile method emulation. In one embodiment, an information processing device includes a host processor 1 for executing predetermined processing and a coprocessor 2 for executing emulation in accordance with a direction from the host processor 1. The coprocessor 2 determines whether the processing to be executed in accordance with emulation is executable by the coprocessor 2 when execution of emulation is directed from the host processor 1. The coprocessor 2 executes the processing when the processing is executable by the coprocessor 2 but leaves execution of the processing to the host processor 1 when the processing is not executable by the coprocessor 2.