Dual-Processor Interrupt Handling for Low-Power Microcontrollers
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Solution Overview
Problem
High power consumption in processors during low activity periods due to leakage currents, which is exacerbated by the large number of transistors in high computational power processors, necessitates a reduction in energy usage without compromising functionality.
Innovation Solution
A dual-processor system where a smaller auxiliary processor takes over during low activity periods, managing a subset of instructions, while the main processor is deactivated, with a power management circuit controlling the switch between the two processors and directing interrupt signals accordingly, and utilizing a volatile and non-volatile memory for storing interrupt routines and vectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the main processor with large number of transistors is used during low activity periods, then the computational power is sufficient, but the leakage current and power consumption become significant
Solution Approach 1:
The system is segmented into two distinct processors: a first processor with high computational power and a second processor with reduced computational power. The power management circuit segments the processing tasks by directing interrupt signals to the appropriate processor based on current activity levels, allowing the system to use only the necessary computational resources for each situation.
Solution Approach 2:
The system changes the operational parameter of computational power by switching between two processors with different transistor counts and processing capabilities. The power management circuit monitors system state and dynamically changes which processor is active, thereby adjusting the computational power parameter to match actual needs and reduce unnecessary power consumption.
2Use of energy by moving object
If the processor is deactivated during low activity periods, then power consumption is reduced, but interrupt handling capability is lost
Solution Approach 1:
The power management circuit acts as an intermediary that monitors interrupt signals and controls the activation of processors. When an interrupt signal is detected, the power management circuit activates the appropriate processor to handle the interrupt, thus maintaining interrupt handling capability while keeping processors deactivated during low activity periods to reduce power consumption.
Solution Approach 2:
The system employs a second processor with reduced functionality that can independently handle basic interrupt signals without requiring the first processor to remain active. This self-service capability allows the system to maintain essential interrupt handling functionality while the high-power first processor remains deactivated, reducing overall power consumption during low activity periods.
3Use of energy by moving object
If a single processor handles all instructions, then the system is simple to implement, but power consumption cannot be optimized for low activity periods
Solution Approach 1:
The power management circuit provides multi-functionality by performing multiple roles: monitoring interrupt signals, controlling processor activation, and directing interrupt signals to the appropriate processor. This universal component enables the system to optimize power consumption without requiring complex control logic distributed across multiple components.
Solution Approach 2:
The system implements dynamic processor selection where the active processor is determined based on real-time system state and interrupt signal characteristics. The power management circuit dynamically switches between the first and second processors depending on whether the interrupt requires high computational power or can be handled by the reduced-power second processor, optimizing energy usage adaptively.
Data Source
AI summary
An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.