Dual Processor System for Power-Constrained Wireless Devices

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Solution Overview

Problem

Portable electronics face increased power consumption and shortened battery life due to high-capacity CPUs handling both CPU-intensive and non-intensive tasks, leading to inefficient power usage, especially with frequent notifications that require minimal CPU capacity.

Innovation Solution

A communication system with a low power front end and high performance applications processor, where a low power connectivity processor handles low-speed connections and non-intensive tasks, and a high performance applications processor is enabled only when necessary for computationally intensive tasks, using a power controller to manage power distribution based on packet type and data rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a high capacity CPU is used to handle all tasks, then the device can meet computational demands for both intensive and non-intensive tasks, but power consumption increases and battery life shortens

Engineering Contradiction:
Improvecomputational capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The system divides processing tasks into two categories handled by separate processors: low-power tasks (notifications, display updates) are handled by a low-capacity CPU, while high-performance tasks (computationally intensive applications) are handled by a high-capacity CPU. This segmentation allows the device to use only the necessary processing power for each task type, reducing overall power consumption while maintaining full computational capability when needed.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If a high capacity CPU is placed in sleep mode when not processing tasks, then power consumption is reduced during idle periods, but power consumption penalty occurs whenever notifications are received requiring CPU activation

Engineering Contradiction:
Improvepower consumption during idle periodsVSAvoidpower consumption penalty on task activation
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system segments CPU functionality into two dedicated processors: a always-on low-capacity CPU handles notifications and wake-up events, preventing the need to fully activate the high-capacity CPU for simple tasks. This eliminates the power consumption penalty associated with frequent wake-sleep cycles of a single high-capacity processor, as the low-capacity CPU remains in a low-power state while still providing essential functionality.

Inventive Principle:
Principle #1Segmentation

3Productivity

If multiple core processors are used to handle various incoming tasks, then task processing capability is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvetask processing capabilityVSAvoidprocessor architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Instead of using multiple cores within a single processor, the system segments functionality into two separate single-core processors with different capability levels. This approach achieves task processing diversity without the complexity of multi-core synchronization and resource management, while also reducing power consumption by keeping the low-capacity CPU as the primary always-on processor.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11537190B2Dual processor system for reduced power application processing
Publication Date: 2022.12.27 SILICON LABORATORIES INC
  • US11537190B2 patent drawing
  • US11537190B2 patent drawing
  • US11537190B2 patent drawing

AI summary

A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.