Dual-Processor Memory Controller Parallel Command Logging

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Solution Overview

Problem

Current memory controllers face inefficiencies due to the overhead of firmware operations, particularly in handling command logging, which limits the ability to operate multiple processors in parallel, thereby reducing performance and increasing latency.

Innovation Solution

A memory controller architecture utilizing two processors, where the first processor generates commands and translates logical addresses, and the second processor performs data operations and logs command information, allowing the first processor to perform other tasks while the second processor handles logging, thus enabling parallel operation and reducing firmware overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single processor handles both command generation and logging operations, then device complexity is reduced, but productivity decreases due to sequential processing

Engineering Contradiction:

Improveprocessing throughputVSAvoidprocessor architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the memory controller into two separate processors: a first processor dedicated to command generation and address translation, and a second processor dedicated to data operations and logging. This segmentation allows parallel execution of different tasks, eliminating the sequential bottleneck and improving overall productivity without significantly increasing device complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a logging buffer as an intermediary component between the two processors. The first processor writes command information to the logging buffer, and the second processor reads from it during idle periods. This intermediary mechanism enables efficient inter-processor communication and data sharing, facilitating parallel operation while maintaining system coherence.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If the first processor performs logging operations, then device complexity is minimized, but loss of time increases due to processor idle periods

Engineering Contradiction:

Improveprocessor idle timeVSAvoidprocessor specialization

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent ensures continuous useful action by designing the second processor to perform logging operations during its idle periods. Instead of leaving the second processor idle, it utilizes its available time to log command information from the logging buffer, thereby eliminating wasted time and improving overall system efficiency.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The second processor serves itself by performing logging operations autonomously during its idle time without requiring intervention from the first processor. This self-service capability allows the logging function to be executed in parallel with data operations, reducing the time loss associated with sequential processing.

Inventive Principle:

Principle #25Self-service

3Productivity

If firmware handles all command processing, then ease of operation is maintained, but productivity decreases due to firmware overhead

Engineering Contradiction:

Improvecommand processing speedVSAvoidfirmware control

Core Design Contradiction:

ProductivityVSEase of operation

Solution Approach 1:

The patent replaces the traditional firmware-based command processing mechanism with a hardware-based dual-processor architecture. The first processor handles command generation and address translation in hardware, while the second processor handles data operations and logging in hardware. This substitution eliminates firmware overhead and significantly improves command processing speed while maintaining ease of operation through standardized interfaces.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11868658B2Memory controller including first processor for generating commands and second processor for generating logging information and method of operating the memory controller

Publication Date: 2024.01.09 SK HYNIX INC

AI summary

A memory controller is configured with a plurality of processors to be operated in parallel so that overhead of firmware may be reduced. The memory controller includes a first processor and a second processor. The first processor is configured to generate a command corresponding to a request received from a host and to translate a logical address included in the request into a physical address of a memory device. The second processor is configured to operate on data to be output to the memory device or on data received from the memory device. If the request is received from the host when the second processor is in an idle state, the first processor may control the second processor to release the idle state of the second processor and to perform an operation of logging command information corresponding to the request.