Dual Processor Memory Ordering Test Circuit
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Solution Overview
Problem
In processors using the relaxed memory ordering (RMO) method, it is challenging to perform accurate order guarantee tests for overtaking accesses to the same address, especially when multiple memory areas are accessed simultaneously, and timing deviations occur between load and store instructions, making it difficult to verify the validity of the order guarantee circuit.
Innovation Solution
An arithmetic processing apparatus with two processors is configured to issue consecutive load instructions and a store instruction, where one processor determines the ordering property based on loaded data, and the other processor synchronizes and alters the store instruction timing to ensure accurate order guarantee testing for overtaking accesses to the same address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory areas are accessed simultaneously during order guarantee test, then test coverage is improved, but timing deviation between load and store instructions occurs making verification difficult
Solution Approach 1:
A dedicated test auxiliary processor is introduced as an intermediary component to coordinate and control the timing of load and store instructions. This mediator processor issues precise control signals to ensure that store instructions are executed at specific timing points during the test, eliminating timing deviations that occur when multiple memory areas are accessed simultaneously by separate processors.
2Measurement precision
If store instruction timing is altered to occur during load instruction execution, then overtaking verification is improved, but test complexity increases
Solution Approach 1:
The test auxiliary processor pre-configures and issues control signals that determine the exact timing of store instruction execution before the actual test begins. By preliminarily establishing the timing schedule and control logic, the system enables precise overtaking verification without requiring complex real-time coordination mechanisms during instruction execution.
Solution Approach 2:
The test auxiliary processor automatically generates and manages the timing control signals for store instructions based on pre-programmed test sequences. This self-service mechanism eliminates the need for external manual timing control or complex inter-processor synchronization protocols, simplifying the overall test control architecture while maintaining precise timing control for overtaking detection.
Data Source
AI summary
An arithmetic processing apparatus includes a memory, a first processor coupled to the memory, and a second processor coupled to the memory. The first processor is configured to consecutively issue a plurality of load instructions for reading respective data with respect to the memory. The first processor is configured to determine whether an ordering property is guaranteed, based on values included in the data loaded from the memory. The second processor is configured to issue a store instruction during an execution of the plurality of load instructions with respect to the memory.