Dual Processor Packet Queuing for Secure Stream Processing
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Solution Overview
Problem
Existing packet processing systems face challenges in efficiently handling security operations, as software-based security processing increases processing load and interferes with real-time requirements, while hardware-based solutions are inflexible and vulnerable to hacking.
Innovation Solution
A system with a separate security processor and dedicated hardware queues for packet queuing, allowing security processing to occur independently of main packet processing, reducing the processing load and vulnerability to hacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based security processing is used, then flexibility and ease of updating security algorithms is improved, but processing load increases and real-time requirements are interfered with
Solution Approach 1:
The system divides packet processing into two separate processors: a first processor for general packet processing and a second processor dedicated to security processing. This segmentation allows each processor to specialize in its function, with the second processor handling security operations independently to avoid interfering with real-time packet processing requirements.
Solution Approach 2:
The security processing function is extracted from the main packet processing path and isolated in a separate second processor. This extraction removes the security processing burden from the real-time packet processing pipeline, allowing the first processor to maintain real-time performance while the second processor handles security operations asynchronously.
2Productivity
If hardware-based security processing is used, then processing speed is improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The second processor is designed as a universal security processing unit that can execute various security algorithms through software. This multi-functional approach allows the system to maintain high processing speed through dedicated hardware architecture while preserving flexibility through software-based algorithm implementation, enabling updates and adaptations without hardware changes.
3Device complexity
If security processing is performed in the main processing path, then processing load is concentrated, but real-time requirements are compromised
Solution Approach 1:
The processing architecture is segmented into two independent processors with dedicated communication queues. The first processor handles packet reception and initial processing, while the second processor handles security operations. This segmentation eliminates the bottleneck of sequential processing and allows parallel execution of packet processing and security operations.
Solution Approach 2:
Dedicated queues are introduced as intermediaries between the two processors, enabling efficient communication and data transfer. These queues act as buffers that decouple the processing steps, allowing the first processor to send packets to the second processor without waiting for security processing completion, thus maintaining real-time performance.
Data Source
AI summary
A system for processing packet streams includes a first packet queuing circuitry connected between a first processor and a second processor and operable to queue packets for transfer from the first processor to the second processor. The system includes a second packet queuing circuitry connected between the first processor and the second processor and operable to queue packets for transfer from the second processor to the first processor. The first processor is programmed to transfer secure packets to the second processor via the first queuing circuitry for security processing and the second processor is programmed to return the security-processed packets to the first processor via the second queuing circuitry.