Dual-Processor Parity Buffer Scheduling for Reduced Storage Delay
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Solution Overview
Problem
Existing storage devices experience time delays in generating and storing parity values, necessitating an efficient method to improve the parity operation process.
Innovation Solution
A storage device with a controller comprising a buffer memory and two processors, where a first processor manages state information of buffer areas and outputs control signals, and a second processor generates and writes parity values based on these signals, optimizing the parity operation by managing buffer area states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single processor is used to generate and store parity values, then the device complexity is reduced, but the time delay in parity operation increases
Solution Approach 1:
The controller is divided into two separate processors: a first processor responsible for managing buffer area state information and generating control signals, and a second processor dedicated to generating and writing parity values. This segmentation allows parallel execution of tasks, reducing the overall time delay in parity operations while maintaining manageable device complexity through clear functional separation.
Solution Approach 2:
The first processor performs preliminary actions by managing buffer area state information in advance and generating control signals before the second processor executes the parity value generation and writing. This preliminary preparation enables the second processor to immediately process parity operations when data is ready, minimizing waiting time and reducing overall operation delay.
2Productivity
If buffer memory is not used for parity storage, then the device structure is simplified, but the parity operation efficiency decreases
Solution Approach 1:
The buffer memory serves multiple functions: it stores data to be written to the memory device, stores generated parity values temporarily, and provides a workspace for the processors to manage state information. This multi-functionality improves parity operation efficiency by eliminating the need for separate dedicated parity memory while maintaining organized and efficient data flow.
Solution Approach 2:
The buffer memory acts as an intermediary between the processors and the main memory device. It temporarily holds parity values after generation and before writing to the main memory, allowing the second processor to complete parity generation independently and efficiently without directly interfacing with the main memory during the critical parity generation phase.
Data Source
AI summary
A first processor manages state information of a buffer area of a buffer memory used as a parity area in a parity operation mode and outputs a control signal according to the state information, and a second processor which performs a parity operation using the buffer area performs the parity operation according to the control signal of the first processor.