Dual Processor Tethering Architecture Reducing Main CPU Load
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Solution Overview
Problem
Tethering between mobile devices and external devices is hindered by high resource utilization of the main processor, leading to increased delay, reduced throughput, power consumption, and heat generation, particularly in 5G networks where high communication speeds are desired.
Innovation Solution
An electronic device with a housing, display, electrical connector, wireless communication circuit, and processors configured to use distinct memory address regions, where a first processor handles data processing and a second processor accesses a shared memory buffer for network transmission, reducing the load on the main processor and optimizing communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the main processor handles all data processing and copying through shared memory, then data transmission functionality is achieved, but processing delay increases and throughput decreases
Solution Approach 1:
The patent divides the processing system into two separate processors: a main processor that handles high-speed data reception from the USB device, and a communication processor that handles network data transmission. This segmentation eliminates the need for data copying through shared memory, allowing each processor to operate independently on its own data buffer, thereby reducing processing delay and increasing tethering speed.
2Productivity
If the main processor is used for data processing, then tethering functionality is implemented, but power consumption increases
Solution Approach 1:
The patent segments the processing workload between two processors, allowing the main processor to focus on high-speed data reception while the communication processor handles network transmission. This division enables the system to maintain tethering functionality while distributing power consumption across both processors, preventing excessive power drain on the main processor.
3Productivity
If the main processor performs extensive data copying and processing, then data transmission is achieved, but heat generation increases
Solution Approach 1:
The patent separates data processing into two independent processing chains using two processors. The main processor handles USB data reception without needing to copy data through shared memory, and the communication processor independently handles network transmission. This segmentation reduces the computational load and memory access operations on the main processor, thereby reducing heat generation while maintaining data transmission capability.
4Adaptability or versatility
If shared memory region is used for data copying between processors, then inter-processor communication is achieved, but overhead increases and performance decreases
Solution Approach 1:
The patent extracts the data copying operation from the processing chain by giving each processor its own dedicated data buffer. The main processor writes directly to its own buffer from the USB device, and the communication processor reads directly from its own buffer to the network interface. This eliminates the need for shared memory copying operations, reducing overhead and simplifying the processing complexity while maintaining inter-processor coordination.
Data Source
AI summary
An electronic device and a tethering method are disclosed. The electronic device includes a housing, and a display exposed through a first portion of the housing. The electronic device also includes an electrical connector exposed through a second portion of the housing, and a wireless communication circuit. The electronic device further includes a first processor operably coupled to the display and the electrical connector and configured to use a first memory address region including a first plurality of addresses. The electronic device also includes a second processor operably coupled to the wireless communication circuit and configured to use a second memory address region including a second plurality of virtual addresses. The electronic device also include an electric circuitry operably coupled to the first processor and the second processor and configured to provide relations between the first plurality of addresses and the second plurality of virtual addresses.