Dual-Processor Serial Transmission for Agreed Vital Data
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Solution Overview
Problem
Vital control systems require a mechanism to ensure that vital data is transmitted serially over a network only if all processors agree on the data content, and protection against the transmission of old or stale data is necessary to prevent invalid messages.
Innovation Solution
A serial communication apparatus with multiple-ported memory accessible by multiple processors, where both processors agree on the data stored in their respective memories before transmitting, and a mechanism to ensure that only agreed-upon data is output, using a buffer that can receive either the message or CRC portion to prevent transmission of invalid data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single processor transmits vital data independently, then transmission speed is improved, but data reliability and integrity are worsened because there is no verification that all processors agree on the data content
Solution Approach 1:
The patent merges multiple processors into a cooperative transmission system where all processors must agree on the data content before transmission. The multiple-ported memory allows all processors to write their determined data and read others' data simultaneously, enabling parallel verification while maintaining a single transmission point that ensures reliability without sacrificing speed.
Solution Approach 2:
The multiple-ported memory acts as an intermediary between multiple processors and the serial communication apparatus. It receives data from multiple processors, enables cross-verification of data content, and facilitates coordinated transmission decisions, thereby ensuring data reliability while maintaining efficient transmission.
2Reliability
If multiple processors independently transmit vital data, then data reliability is improved through verification, but transmission coordination and system complexity are worsened
Solution Approach 1:
The patent combines multiple processors and a multiple-ported memory into an integrated system where verification and transmission functions are merged. This unified architecture reduces coordination overhead compared to fully distributed transmission, as all processors write to shared memory and a single serial communication apparatus handles transmission, simplifying the overall system while maintaining reliability.
Solution Approach 2:
The multiple-ported memory serves multiple functions simultaneously: it stores data from multiple processors, enables cross-verification of data content, and facilitates coordinated access by the serial communication apparatus. This multi-functionality reduces the need for separate verification and transmission components, lowering system complexity.
3Reliability
If a communication protocol provides protection against stale data transmission, then data freshness is improved, but protocol complexity and processing overhead are worsened
Solution Approach 1:
The patent performs preliminary verification of data freshness by requiring all processors to determine and write their current data to the multiple-ported memory before transmission. This advance verification ensures that only up-to-date data is transmitted, eliminating the need for complex runtime protocol checks and reducing processing overhead during actual transmission.
Solution Approach 2:
The system uses its own multiple-ported memory structure to automatically verify data freshness through coordinated write and read operations by multiple processors. This self-verification mechanism eliminates the need for external protocol-based stale data protection, simplifying the communication protocol while maintaining data freshness.
4Reliability
If all processors must agree on data content before transmission, then data integrity is improved, but transmission latency is worsened due to coordination requirements
Solution Approach 1:
The patent maintains continuous useful action by allowing all processors to simultaneously write their data to the multiple-ported memory while the serial communication apparatus continuously monitors for agreement. This parallel operation ensures that verification occurs without idle waiting periods, reducing transmission latency while maintaining data integrity through coordinated agreement.
Solution Approach 2:
Processors perform preliminary data determination and writing to the multiple-ported memory before the transmission decision is made. This advance preparation ensures that when all processors agree on the data content, the transmission can occur immediately without additional coordination delays, reducing overall transmission latency while ensuring data integrity.
Data Source
AI summary
A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.