Dual Program State Cycling for Resistive Switching Memory
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Solution Overview
Problem
Flash memory technologies face limitations such as high power consumption and slow operation speed, while resistive switching memory technologies like ReRAM and CBRAM offer lower power and higher speeds but face degradation issues during high-temperature processes like surface-mount technology (SMT) processes.
Innovation Solution
The implementation of programmable impedance elements in resistive switching memory devices, such as CBRAM, which can be programmed and erased between resistance states using symmetric operations without external charge pumps, and employing dual program states with weak and strong programming algorithms to maintain data integrity during SMT processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If flash memory technology is used, then storage capacity is achieved, but power consumption is high and operation speed is slow
Solution Approach 1:
The patent changes the physical state parameters of the memory cell by utilizing resistive switching between high resistance state (HRS) and low resistance state (LRS). This allows the memory device to achieve faster operation speeds and lower power consumption compared to flash memory, as the resistive switching mechanism enables quicker state transitions and reduces the energy required for write operations.
2Speed
If resistive switching memory technology is used, then power consumption is reduced and operation speed is increased, but data state degradation occurs during high-temperature processes
Solution Approach 1:
The patent applies preliminary action by performing a control erase operation before the SMT process and a control program operation after the SMT process. This preventive approach ensures that any potential data state degradation during high-temperature processing is compensated for, thereby maintaining data integrity and reliability throughout the manufacturing and operation lifecycle.
Solution Approach 2:
The patent implements feedback mechanisms through verify operations that check the resistance states of memory cells. By continuously monitoring and verifying the data states before and after SMT processes, the system can detect and correct any degradation, ensuring reliable operation despite the harsh thermal conditions encountered during manufacturing.
3Reliability
If dual program states are implemented, then data integrity is maintained during SMT processes, but device complexity increases
Solution Approach 1:
The patent segments the programming process into distinct phases: control erase operation, control program operation, and verify operations. By dividing the complex dual-program-state management into manageable sequential steps, the system maintains data integrity during SMT processes while keeping the implementation complexity manageable through structured process segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient programming and erasing of resistive memory cells with improved retention and reduced risk of data state degradation during high-temperature processes, maintaining data integrity and operational margins between states.
Implementation Method 1
resistive switching memory technologies that include resistive RAM (ReRAM) and conductive bridging RAM (CBRAM)
Data Source
AI summary
A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.