Dual-Protocol Link Controller for PCIe and Gen-Z Interoperability
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Solution Overview
Problem
Existing system interconnect standards, such as PCIe, face challenges in multi-processor systems where memory sharing and compatibility with older standards are concerns, leading to increased memory capacity requirements and potential obsolescence of system components.
Innovation Solution
A dual-protocol link controller is introduced, which includes a PCIe physical layer circuit, data link layer controllers for both PCIe and Gen-Z protocols, a multiplexer-demultiplexer, and a protocol translation circuit. This allows for seamless communication between processors and memory modules using either the PCIe or Gen-Z protocol, ensuring compatibility and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new interconnect standards are adopted to improve communication speed and capacity in multi-processor systems, then memory capacity requirements increase and system performance improves, but compatibility with older standards deteriorates and system components become obsolete
Solution Approach 1:
The link controller is designed to support multiple protocols (PCIe and Gen-Z) simultaneously, making it universally compatible with both older and newer standards. This allows a single controller to handle diverse protocol requirements without requiring separate dedicated controllers for each protocol type.
Solution Approach 2:
A protocol translation circuit is introduced as an intermediary component that translates between PCIe and Gen-Z protocols. This mediator enables communication between systems using different protocols without requiring direct compatibility between the protocols themselves, resolving the compatibility issue.
2Adaptability or versatility
If dual-protocol link controller is introduced to maintain compatibility with older standards, then protocol compatibility improves, but device complexity increases
Solution Approach 1:
The patent combines multiple protocol handling capabilities into a single link controller by integrating both PCIe and Gen-Z data link layer controllers, along with protocol translation circuitry. This merging approach consolidates what would otherwise require separate controllers into one unified device.
Solution Approach 2:
The link controller is designed to support multiple protocols (PCIe and Gen-Z) simultaneously, making it universally compatible with both older and newer standards. This allows a single controller to handle diverse protocol requirements without requiring separate dedicated controllers for each protocol type.
3Adaptability or versatility
If PCIe protocol is used for communication, then backward compatibility with existing systems is maintained, but support for newer memory standards and architectures is limited
Solution Approach 1:
The link controller dynamically switches between PCIe and Gen-Z protocols based on the memory module capabilities and system requirements. This dynamic protocol selection allows the system to adapt to different memory standards, using PCIe for backward compatibility and Gen-Z for enhanced capacity when needed.
Solution Approach 2:
A protocol translation circuit is introduced as an intermediary component that translates between PCIe and Gen-Z protocols. This mediator enables communication between systems using different protocols without requiring direct compatibility between the protocols themselves, resolving the compatibility issue.
Data Source
AI summary
A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.


