Dual-Pulse Clocked Storage Circuit for Faster Low-Capacitance Switching
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Solution Overview
Problem
Conventional clock-based data storage devices suffer from high internal capacitance, which slows down switching speed and leads to increased power consumption due to inefficient control of pull-up and pull-down signals using a single dynamic node.
Innovation Solution
A clock-based data storage device employing a dual pulse generating unit that outputs two clock signals, allowing a pull-up unit and a pull-down unit to control output signals independently using previously charged and discharged dynamic nodes, respectively, thereby reducing internal capacitance and improving switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single dynamic node is used to control both pull-up and pull-down signals, then the circuit structure is simplified, but internal capacitance increases and switching speed decreases
Solution Approach 1:
The patent divides the single dynamic node into two separate dynamic nodes: a first dynamic node for controlling the pull-up signal and a second dynamic node for controlling the pull-down signal. This segmentation reduces the internal capacitance that would otherwise be accumulated in a single shared node, thereby improving switching speed while maintaining circuit functionality.
Solution Approach 2:
The patent extracts the pull-up and pull-down control functions from a single shared dynamic node into separate dedicated nodes. By taking out the coupled capacitance burden from the original single node design, each dynamic node operates with reduced internal capacitance, enabling faster switching performance.
2Device complexity
If a single dynamic node is used for both pull-up and pull-down control, then the number of circuit elements is reduced, but power consumption increases due to power leakage
Solution Approach 1:
The patent segments the power control paths by providing separate dynamic nodes for pull-up and pull-down operations. This segmentation prevents power leakage that occurs in the stacked transistor configuration of conventional designs, as each dynamic node independently controls its respective transistor without the harmful interaction of shared capacitance.
Solution Approach 2:
The patent extracts the power leakage issue from the conventional stacked structure by separating the pull-up and pull-down control into independent dynamic nodes. This extraction eliminates the power consumption problem associated with the shared dynamic node and stacked transistor configuration.
3Ease of manufacture
If conventional Flip Flop structure with stacked transistors is used, then the circuit implementation is straightforward, but operational speed decreases due to discharging path resistance
Solution Approach 1:
The patent segments the transistor arrangement by connecting the source of the first output transistor to the drain of the second output transistor, rather than using a stacked configuration. This segmentation creates independent discharge paths that reduce resistance and improve operational speed while maintaining ease of implementation.
Solution Approach 2:
The patent inverts the conventional stacked transistor connection by reversing the source-drain relationship between the first and second output transistors. This inversion creates a more efficient current path that reduces discharging resistance and improves operational speed.
Data Source
AI summary
Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding to inversion of a clock signal and a second clock signal corresponding to the clock signal by using the delayed clock signal when the clock signal shifts, a pull-up wait for outputting a pull-up output signal to an output port, based on the first clock signal outputted from the dual pulse generating unit and an input data signal which has beeb inputted, a pull-down unit for outputting a pull-down output signal to the output port, based on the second clock signal outputted from the dual pulse generating unit and the input data signal inputted which has been inputted, and a latch unit which is disposed between the pull-up and pull-down units, and the output port so as to store at least one output signal outputted from the pull-down unit as well as the pull-down unit.