Dual-Purpose On-Chip Buffer Memory for Low Latency Switching
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Solution Overview
Problem
Typical network switches experience latency due to the resource-intensive process of searching through large look-up tables to determine packet paths, which can slow down data switching across networks.
Innovation Solution
Implementing a dual-purpose on-chip buffer memory that stores look-up tables and buffers packets, utilizing heuristics-based flow learning to reduce latency by partitioning the memory for efficient packet switching and storing look-up tables in a first portion, with the ability to buffer packets in another portion, and using a timer-based flow expiration mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large look-up table is used to store packet path information, then routing accuracy is improved, but switching latency increases due to resource-intensive search operations
Solution Approach 1:
The patent divides the buffer memory into distinct portions: a first portion for storing look-up tables and a second portion for packet buffering. This segmentation allows the look-up table search operations to be performed in a dedicated memory space optimized for fast access, while packet buffering occurs in a separate area, thereby reducing switching latency while maintaining routing accuracy.
Solution Approach 2:
The patent combines the look-up table storage and packet buffering functions into a single on-chip buffer memory unit. By merging these two functions that were traditionally separate, the system achieves faster access to routing information while efficiently utilizing on-chip memory resources, thus reducing switching latency without compromising routing accuracy.
2Productivity
If separate memory units are used for look-up tables and packet buffering, then functional performance is improved, but device complexity and resource utilization worsen
Solution Approach 1:
The on-chip buffer memory is designed as a universal memory structure that performs multiple functions: storing look-up tables, buffering packets, and supporting both read and write operations. This multi-functional design eliminates the need for separate dedicated memory units, reducing device complexity while maintaining high switching efficiency through unified memory management.
Solution Approach 2:
The patent organizes the memory space with look-up tables in a first portion and packet buffers in a second portion, creating a spatial dimension separation within the unified memory structure. This dimensional organization allows efficient access patterns for both routing look-ups and packet buffering operations simultaneously, achieving high productivity without increasing structural complexity.
Data Source
AI summary
In one embodiment, an apparatus includes a buffer memory, at least one ingress port, at least one egress port, at least one processor, and logic integrated with and/or executable by the at least one processor, the logic being configured to communicate with a software-defined network (SDN) controller, store one or more look-up tables in a first portion of the buffer memory, receive a packet using an ingress port, and determine an egress port for the packet. In another embodiment, a method for switching packets in a SDN includes storing one or more look-up tables in a first portion of a buffer memory of a SDN-capable switching device, receiving a packet using an ingress port of the switching device, and determining an egress port for the packet.