Dual Purpose Data Valid Signal in Non-Volatile Memory
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Solution Overview
Problem
Current NAND flash memory systems lack an efficient method for the memory controller to determine when block erase or write operations are completed, leading to inefficiencies such as time-consuming polling or increased pin count for completion signals.
Innovation Solution
The proposed solution involves using a shared signal line, like the Data Valid (DV) line, to indicate operation completion during block write and erase operations, allowing the memory controller to perform other tasks while the operation is in progress and enabling identification of the completing device through polling if multiple devices share the line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a separate signal line is dedicated to each memory device to indicate operation completion, then the memory controller can efficiently detect completion, but the pin count increases and space is consumed
Solution Approach 1:
The patent applies multi-functionality by enabling a single shared signal line to serve multiple purposes: it indicates operation completion for any of the multiple memory devices connected to the bus, replacing the need for separate dedicated signal lines for each device. The memory controller detects completion status by monitoring this shared line, which any memory device can assert when its operation completes.
2Measurement precision
If the memory controller periodically polls the memory device to check operation completion, then completion status can be determined, but time is consumed and efficiency is reduced
Solution Approach 1:
The patent implements feedback by having memory devices actively assert a signal on the shared signal line when their block write or erase operations complete. This creates an automatic notification mechanism where the memory device itself provides completion status information to the memory controller, eliminating the need for continuous polling and reducing the time the controller spends waiting for operation completion.
3Reliability
If the memory controller waits for operation completion before performing other tasks, then operation status is known, but bandwidth is reduced and time is lost
Solution Approach 1:
The patent applies preliminary action by allowing the memory controller to initiate block write or erase operations on multiple memory devices and then immediately proceed with other tasks without waiting for completion. The controller uses the shared signal line to receive completion notifications asynchronously, enabling it to maintain high bandwidth utilization by overlapping operation execution with other controller activities.
Data Source
AI summary
In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used by a memory controller to latch the data that is being received from the memory device. During a block erase operation and/or a block write operation, the signal may be used to notify the memory controller that the operation has been completed by the memory device.