Dual Queue Processor Interrupt Management

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Solution Overview

Problem

Current processor technologies face challenges in efficiently managing resources associated with interrupts for input/output commands from virtual devices, particularly in handling process address space identifiers (PASID) using existing queue management methods.

Innovation Solution

A processor employing dual queues to manage interrupts, where one queue stores PASID-specific interrupts and another stores corresponding data and location information, allowing for efficient allocation and eviction of resources based on calculated weights.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single queue is used to manage interrupts from virtual devices, then the device complexity is reduced, but the productivity of interrupt handling decreases due to inefficient resource allocation

Engineering Contradiction:
Improveinterrupt handling efficiencyVSAvoidqueue management structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The interrupt management system is segmented into two separate queues: a first queue for storing interrupt information (including PASID) and a second queue for storing data and location information. This segmentation allows independent optimization of interrupt handling and data management, improving overall productivity without excessive complexity increase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from a single-dimensional queue structure to a two-dimensional dual-queue structure, where the first queue handles interrupt prioritization and the second queue handles data storage. This dimensional change enables more efficient resource allocation and interrupt handling performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of information

If interrupts are stored with complete data in a single queue, then the loss of information is minimized, but the device complexity increases due to unified management requirements

Engineering Contradiction:
Improveinterrupt data completenessVSAvoidqueue management structure
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

Complete interrupt information is preserved by segmenting it across two queues: the first queue stores interrupt identifiers and PASID for tracking, while the second queue stores the actual data and location information. This segmentation maintains data completeness while simplifying management operations in each queue.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first queue acts as an intermediary between interrupt sources and the second queue, managing interrupt prioritization and routing. This intermediary structure preserves all interrupt information while distributing management complexity across two specialized queues rather than one complex queue.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If resource allocation is done without prioritization, then the ease of operation is maximized, but the productivity of virtual device I/O decreases

Engineering Contradiction:
ImproveI/O command handling speedVSAvoidresource allocation complexity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

Interrupt prioritization is performed in advance when interrupts are stored in the first queue, before data processing occurs. This preliminary action ensures that high-priority I/O commands are handled first, improving productivity without adding complexity during the actual data processing phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter of interrupt management by introducing priority levels and PASID-based identification. This parameter change enables differentiated resource allocation that improves I/O handling speed while maintaining operational simplicity through automated queue management.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If memory space is allocated for all possible interrupts, then the reliability of interrupt handling is ensured, but the loss of substance (memory resources) increases

Engineering Contradiction:
Improveinterrupt handling guaranteeVSAvoidmemory resource usage
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

Memory allocation becomes dynamic through the dual-queue structure, where the first queue maintains compact interrupt metadata and the second queue allocates data storage space as needed. This dynamic allocation ensures reliable interrupt handling while minimizing memory usage by only allocating space for actual interrupts that occur.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system efficiently manages memory by allocating space in the second queue only when interrupts are actually present and need processing. Memory resources are recovered and reused as interrupts are processed, ensuring reliability for active interrupts while minimizing overall memory consumption.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20230266992A1Processor for managing resources using dual queues, and operating method thereof
Publication Date: 2023.08.24 SAMSUNG ELECTRONICS CO LTD
  • US20230266992A1 patent drawing
  • US20230266992A1 patent drawing
  • US20230266992A1 patent drawing

AI summary

A method for managing resources by using a processor that includes a first queue and a second queue includes receiving, by the processor, input/output commands from a virtual device, generating, by the processor, interrupts that each includes a process address space identifier (PASID) that corresponds to each of the input/output commands, storing, by the processor, the interrupts in the first queue, storing, by the processor, in a memory device, data that respectively corresponds to each of the interrupts, and storing, by the processor, in the second queue, location information indicating a storage location of the data stored in the memory device and size information indicating a size of the data.