Semiconductor Storage Data Latch with Dual-Rail Wiring
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in improving interface performance, particularly in data transfer efficiency and reliability between memory cells, bit lines, and sense amplifier circuits.
Innovation Solution
The semiconductor storage device incorporates a data latch circuit with a first and second data wiring to transfer mutually inverted data signals, utilizing a first node for data storage and a second node for inverted data storage, enhancing data transfer efficiency and reliability through improved signal inversion and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional data latch circuit is used, then the device complexity is lower, but the interface performance and data transfer efficiency are insufficient
Solution Approach 1:
The data latch circuit is segmented into multiple independent latch units (first data latch circuit and second data latch circuit), each handling specific data paths. This segmentation allows parallel operation for improved data transfer efficiency while keeping each individual latch unit relatively simple in structure.
Solution Approach 2:
The patent introduces a dual-rail architecture where data is transmitted through two complementary paths (first data wiring and second data wiring with inverted signals). This dimensional expansion from single-path to dual-path transmission enables simultaneous data and clocking functions, improving interface performance without significantly increasing overall system complexity.
2Reliability
If mutual inversion of data signals is implemented, then data transfer reliability is improved, but the device complexity increases due to additional wiring and circuits
Solution Approach 1:
The patent merges the data signal transmission and clocking functions into a unified dual-rail system. The first and second data wirings carry both data information and timing synchronization signals simultaneously, eliminating the need for separate clock lines and reducing overall wiring complexity despite the mutual inversion requirement.
Solution Approach 2:
The complementary nature of the first and second data signals allows the system to self-synchronize without external clock inputs. The mutual inversion relationship between the two wirings automatically provides timing reference and synchronization information, enabling the circuit to regulate its own operation and reducing the need for additional control wiring.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier circuit electrically connected to the bit line, a first data wiring electrically connected to the sense amplifier circuit, a data latch circuit electrically connected to the first data wiring, and a second data wiring and a third data wiring electrically connected to the data latch circuit, for transferring mutually inverted data signals. The data latch circuit includes a first node that stores data and a second node that stores inverted data of the data. The second data wiring is electrically connected to the first node. The first data wiring and the third data wiring are electrically connected to the second node.