Dual-Rail Delay Chain Initialization for Precise Voltage-to-Time Conversion
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Solution Overview
Problem
Conventional voltage-to-time conversion techniques in integrated circuits face challenges in accurately determining power supply voltage, leading to improper operation due to measurement inaccuracies or inefficient power management, as they rely on single-sided delay chains that may not provide sufficient precision or simultaneous data and complement signals.
Innovation Solution
A dual-sided delay chain circuit with cross-coupled inverters that interconnect two rails, enhancing resolution and reducing metastability, allowing for simultaneous data and complement signals to be propagated, thereby improving the precision of power supply voltage determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single-sided delay chains are used for voltage-to-time conversion, then the device complexity is reduced, but the measurement precision of power supply voltage deteriorates
Solution Approach 1:
The patent transitions from a single-sided delay chain to a dual-sided delay chain structure. The dual-sided structure includes two separate delay chains (first and second delay chains) that operate in parallel, each processing signals in opposite directions. This dimensional expansion from single-sided to dual-sided architecture enables simultaneous generation of data and complement signals with matched phases, thereby improving voltage measurement precision without excessive complexity increase.
Solution Approach 2:
The delay chain is segmented into two independent but coordinated chains: a first delay chain processing the data signal and a second delay chain processing the complement signal. Each chain is initialized separately with controlled signal propagation speeds. This segmentation allows independent optimization of each chain's performance while maintaining overall system precision.
2Reliability
If standard flip-flop components with internal data complement generation are used, then the device complexity is reduced, but the reliability due to metastability deteriorates
Solution Approach 1:
The initialization circuit generates the data and complement signals with matched phases before they are fed into the flip-flop component. By pre-synchronizing the signals and ensuring they transition simultaneously, the circuit eliminates metastability conditions that would otherwise occur within the flip-flop. This preliminary action of signal matching prevents reliability issues before they can manifest.
Solution Approach 2:
The initialization circuit acts as an intermediary between the delay chains and the flip-flop component. It receives signals from both delay chains, synchronizes their phases, and ensures they are matched before presenting them to the flip-flop. This intermediary function eliminates the need for internal complement generation within the flip-flop while maintaining signal integrity and reducing metastability.
3Measurement precision
If inverters of uniform size are used in the delay chain, then the manufacturing precision is simplified, but the measurement precision of voltage-to-time conversion deteriorates
Solution Approach 1:
The patent applies different inverter sizes at different locations within the delay chain structure. Specifically, the first and second inverters in the initialization circuit are sized differently to control signal propagation speeds in opposite directions. This local variation in inverter quality (size) creates the necessary asymmetric signal timing control while maintaining overall manufacturing feasibility through standardized design rules.
Data Source
AI summary
A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.